Datasheet

63
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
13.3.3 EIFR – External Interrupt Flag Register
• Bit 7 – PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in
SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Note: 1. This bit is a reserved bit in the Atmel ATmega169A/169PA/329A/329PA/649A/649P and will always be read as zero.
• Bit 6 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT24:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in
SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Note: 1. This bit is a reserved bit in ATmega169A/169PA/329A/329PA/649A/649P and will always be read as zero.
• Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in
SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 4 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in
SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
Bit 76543210
0x1C (0x3C) PCIF3
(1)
PCIF2
(1)
PCIF1 PCIF0 – – – INTF0 EIFR
Read/Write R/W R/W R/W R/W R R R R/W
Initial Value00000000