Datasheet

61
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
13.2 Pin change interrupt timing
An example of timing of a pin change interrupt is shown in Figure 13-1.
Figure 13-1. Pin change interrupt.
13.3 Register description
13.3.1 EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 13-1 on
page 62. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected,
pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to gener-
ate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
clk
PCINT(n)
pin_lat
pin_sync
pcint_in_(n)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn
pin_lat
D Q
LE
pcint_setflag
PCIF
clk
clk
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
Bit 76543210
(0x69)
– – – – – – ISC01 ISC00 EICRA
Read/Write RRRRRRR/WR/W
Initial Value00000000