Datasheet

43
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
10.10.6 Port pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then
to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
I/O
) and the ADC clock
(clk
ADC
) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it
will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 69 for details on which
pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level
close to V
CC
/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V
CC
/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on
page 205 and ”DIDR1 – Digital Input Disable Register 1” on page 205 for details.
10.10.7 JTAG interface and On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep
mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total
current consumption. There are three alternative ways to avoid this:
• Disable OCDEN Fuse
• Disable JTAGEN Fuse
• Write one to the JTD bit in MCUCSR
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data.
If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase. Note
that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit
in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface.