Datasheet

ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]

8284E–AVR–02/2013

9.11 Register Description

9.11.1 OSCCAL – Oscillator Calibration Register

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process varia-

tions from the oscillator frequency. A pre-programmed calibration value is automatically written to this register

during chip reset, giving the Factory calibrated frequency as specified in Table 29-12 on page 333. The application

software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies

as specified in Table 29-12 on page 333. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected

accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM

or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency

range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other

words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL6...0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest fre-

quency in that range, and a setting of 0x7F gives the highest frequency in the range.

9.11.2 CLKPR – Clock Prescale Register

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated

when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after

it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither

extend the time-out period, nor clear the CLKPCE bit.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3:0

These bits define the division factor between the selected clock source and the internal system clock. These bits

can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the

master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.

The division factors are given in Table 9-14 on page 38.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the

CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will

be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start

Bit 76543210

(0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value Device Specific Calibration Value

Bit 76543210

(0x61)

CLKPCE

– – –

CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description