Datasheet

35
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure
stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to
unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock
frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency
while still ensuring stable operation. Refer to ”System Clock Prescaler” on page 35 for details.
9.8 Clock Output Buffer
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is suitable when the
chip clock is used to drive other circuits on the system. The clock will be output also during reset and the normal
operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including internal RC Oscil-
lator, can be selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is the divided
system clock that is output when the CKOUT Fuse is programmed.
9.9 Timer/Counter Oscillator
Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P uses the same XTAL oscillator
for Low-frequency Oscillator and Timer/Counter Oscillator. See ”Low-frequency XTAL oscillator” on page 32 for
details on the oscillator and XTAL requirements.
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P share the Timer/Counter Oscillator
Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock
needs to be four times the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can
only be used when the Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one.
See ”Asynchronous operation of Timer/Counter2” on page 151 for further description on selecting external clock as
input instead of a 32.768kHz watch XTAL.
9.10 System Clock Prescaler
The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P system clock can be divided by
setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the
requirement for processing power is low. This can be used with all clock source options, and it will affect the clock
frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
ADC
, clk
CPU
, and clk
FLASH
are divided by a factor as
shown in Table 9-14 on page 38.
9.10.1 Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock
system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous
setting, nor the clock frequency corresponding to the new setting.
Table 9-13. Start-up times for the external clock selection.
SUT1..0
Start-up time from power-
down and power-save
Additional delay from
reset (V
CC
= 5.0V) Recommended usage
00 6CK 14CK BOD enabled
01 6CK 14CK + 4.1ms Fast rising power
10 6CK 14CK + 65ms Slowly rising power
11 Reserved