Datasheet

335
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
29.8 SPI Timing Characteristics
See Figure 29-4 on page 335 and Figure 29-5 on page 336 for details.
Notes: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
< 12MHz
- 3 t
CLCL
for f
CK
> 12MHz
Figure 29-4. SPI interface timing requirements (Master mode).
Table 29-17. SPI timing parameters.
Description Mode Min. Typ. Max. Units
1 SCK period Master See Table 19-5 on page 166
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5Hold Master 10
6 Out to SCK Master 0.5 • t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9SS
low to out Slave 15
10 SCK period Slave 4 • t
ck
11 SCK high/low
(1)
Slave 2 • t
ck
12 Rise/Fall time Slave 1.6 µs
13 Setup Slave 10
ns
14 Hold Slave t
ck
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS
low to SCK Slave 20 • t
ck
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSBLSB
LSBMSB
...
...
61
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