Datasheet

297
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
28.6 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Mem-
ory Lock bits, and Fuse bits in the
Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P. Pulses are assumed to be at
least 250ns unless otherwise noted.
28.6.1 Signal Names
In this section, some pins of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P are
referenced by signal names describing their functionality during parallel programming, see Figure 28-1 on page
297 and Table 28-9 on page 297. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is
shown in Table 28-11 on page 298.
When pulsing WR
or OE, the command loaded determines the action executed. The different Commands are
shown in Table 28-12 on page 298.
Figure 28-1. Parallel programming.
Table 28-9. Pin name mapping.
Signal name in
programming mode Pin name I/O Function
RDY/BSY
PD1 O
0: Device is busy programming, 1: Device is ready for
new command.
OE PD2 I Output Enable (Active low).
WR
PD3 I Write Pulse (Active low).
BS1 PD4 I
Byte Select 1 (“0” selects low byte, “1” selects high
byte).
XA0 PD5 I XTAL Action Bit 0
XA1 PD6 I XTAL Action Bit 1
VCC
+5V
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
PB7 - PB0 DATA
RESET
PD7
+12 V
BS1
XA0
XA1
OE
RDY/BSY
PAGEL
PA0
WR
BS2
AVCC
+5V