Datasheet

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ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are cor-
rectly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be
written to one before a logical one is written to EEWE, oth
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in
the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read
access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the
CPU is halted for four cycles before the next instruction is executed.
8.6.5 GPIOR2 – General Purpose I/O Register 2
8.6.6 GPIOR1 – General Purpose I/O Register 1
8.6.7 GPIOR0 – General Purpose I/O Register 0
Bit 76543210
0x2B (0x4B) MSB LSB GPIOR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x2A (0x4A) MSB LSB GPIOR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x1E (0x3E) MSB LSB GPIOR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0