Datasheet

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ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
8.4 I/O memory
The I/O space definition of the Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P
is shown in ”Register summary” on page 871.
All ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P I/Os and peripherals are placed in
the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring
data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits
can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When address-
ing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a complex microcontroller with
more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instruc-
tions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions
can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such
Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
8.5 General purpose I/O registers
The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P contains three General Purpose
I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing
global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
8.6 Register description
8.6.1 EEARH and EEARL – EEPROM address register Atmel ATmega169A/169PA
• Bits 15:9 – Reserved
These bits are reserved and will always be read as zero.
• Bits 8:0 – EEAR8:0: EEPROM address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM
space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined.
A proper value must be written before the EEPROM may be accessed.
Bit 151413121110 9 8
0x22 (0x42)
– – – – – – – EEAR8 EEARH
0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
765 4 3 2 1 0
Read/Write R R R R R R R R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 X
XXX X X X X X