Datasheet

236
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
The frame frequency can be calculated by the following equation:
Where:
N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048 or 4096).
K = 8 for duty = 1/4, 1/2 and static.
K = 6 for duty = 1/3.
D = Division factor (see Table 24-5 on page 236).
This is a very flexible scheme, and users are encouraged to calculate their own table to investigate the possible
frame rates from the formula above. Note when using 1/3 duty the frame rate is increased with 33% when Frame
Rate Register is constant. Example of frame rate calculation is shown in Table 24-6 on page 236.
24.5.4 LCDCCR – LCD Contrast Control Register
• Bits 7:5 – LCDDC[2:0]: LDC Display Configuration
The LCDDC[2:0] bits determine the amount of time the LCD drivers are turned on for each voltage transition on
segment and common pins. A short drive time will lead to lower power consumption, but displays with high internal
Table 24-5. LCD clock divide
LCDCD2 LCDCD1 LCDCD0
Output from
Prescaler
divided by (D):
clk
LCD
= 32.768kHz, N = 16, and Duty =
1/4, gives a frame rate of:
0 0 0 1 256Hz
0 0 1 2 128Hz
010 3 85.3Hz
0 1 1 4 64Hz
100 5 51.2Hz
101 6 42.7Hz
110 7 36.6Hz
1 1 1 8 32Hz
Table 24-6. Example of frame rate calculation.
clk
LCD
duty K N LCDCD2:0 D Frame rate
4MHz 1/4 8 2048 011 4 4000000/(8×2048×4) = 61Hz
4MHz 1/3 6 2048 011 4 4000000/(6×2048×4) = 81Hz
32.768kHz Static 8 16 000 1 32768/(8×16×1) = 256Hz
32.768kHz 1/2 8 16 100 5 32768/(8×16×5) = 51Hz
f
frame
f
clk
LCD
KND
------------------------- -=
Bit 7 6 543210
(0xE7)
LCDDC2 LCDDC1 LCDDC0 LCDNDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 LCDCCR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0