Datasheet

235
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Note: 1. LCDPM3 is reserved and will always read as zero in Atmel ATmega329A/329PA/649A/649P.
24.5.3 LCDFRR – LCD Frame Rate Register
• Bit 7 – Reserved Bit
This bit is reserved and will always read as zero.
• Bits 6:4 – LCDPS[2:0]: LCD Prescaler Select
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further divided by setting the
clock divide bits (LCDCD[2:0]). The different selections are shown in Table 24-4 on page 235. Together they deter-
mine the prescaled LCD clock (clk
LCD_PS
), which is clocking the LCD module.
• Bit 3 – Reserved
This bit is reserved and will always read as zero.
• Bits 2:0 – LCDCD[2:0]: LCD Clock Divide 2, 1, and 0
The LCDCD[2:0] bits determine division ratio in the clock divider. The various selections are shown in Table 24-5
on page 236. This Clock Divider gives extra flexibility in frame rate selection.
1001 SEG0:28 29
1010 SEG0:30 31
1011 SEG0:32 33
1100 SEG0:34 35
1101 SEG0:36 37
1110 SEG0:38 39
1111 SEG0:39 40
Table 24-3. LCD Port Mask (Values in bold are only available in the Atmel
ATmega3290A/3290PA/6490A/6490P) (Continued)
LCDPM3 LCDPM2 LCDPM1 LCDPM0 I/O port in use as segment driver Maximum number of segments
Bit 76543210
(0xE6)
–
LCDPS2 LCDPS1 LCDPS0
–
LCDCD2 LCDCD1 LCDCD0 LCDFRR
Read/Write R R/W R/W R/W R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 24-4. LCD prescaler select.
LCDPS2 LCDPS1 LCDPS0
Output from
prescaler clk
LCD
/N
Applied prescaled LCD clock frequency when
LCDCD2:0 = 0, Duty = 1/4, and Frame Rate = 64Hz
000 clk
LCD
/16 8.1kHz
001 clk
LCD
/64 33kHz
010 clk
LCD
/128 66kHz
011 clk
LCD
/256 130kHz
100 clk
LCD
/512 260kHz
101 clk
LCD
/1024 520kHz
110 clk
LCD
/2048 1MHz
111 clk
LCD
/4096 2MHz