Datasheet

234
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
24.5.2 LCDCRB – LCD Control and Status Register B
Note: Bit 3, LCDPM3 is only available in Atmel ATmega3290A/3290PA/6490A/6490P.
• Bit 7 – LCDCS: LCD Clock Select
When this bit is written to zero, the system clock is used. When this bit is written to one, the external asynchronous
clock source is used. The asynchronous clock source is either Timer/Counter Oscillator or external clock, depend-
ing on EXCLK in ASSR. See ”Asynchronous operation of Timer/Counter2” on page 151 for further details.
• Bit 6 – LCD2B: LCD 1/2 Bias Select
When this bit is written to zero, 1/3 bias is used. When this bit is written to one, ½ bias is used. Refer to the LCD
Manufacture for recommended bias selection.
• Bit 5:4 – LCDMUX[1:0]: LCD Mux Select
The LCDMUX[1:0] bits determine the duty cycle. Common pins that are not used are ordinary port pins. The differ-
ent duty selections are shown in Table 24-2 on page 234.
Note: 1. 1/2 bias when LCD2B is written to one and 1/3 otherwise.
• Bits 3:0 – LCDPM[3:0]: LCD Port Mask
The LCDPM3:0 bits determine the number of port pins to be used as segment drivers. The different selections are
shown in Table 24-3 on page 234. Unused pins can be used as ordinary port pins.
Bit 765 4 3210
(0xE5)
LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 LCDCRB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value000 0 0000
Table 24-2. LCD duty select.
LCDMUX1 LCDMUX0 Duty Bias COM pin I/O port pin
0 0 Static Static COM0 COM1:3
0 1 1/2 1/2 or 1/3
(1)
COM0:1 COM2:3
101/31/2
or 1/3
(1)
COM0:2 COM3
111/41/2
or 1/3
(1)
COM0:3 None
Table 24-3. LCD Port Mask (Values in bold are only available in the Atmel
ATmega3290A/3290PA/6490A/6490P)
LCDPM3 LCDPM2 LCDPM1 LCDPM0 I/O port in use as segment driver Maximum number of segments
0000 SEG0:12 13
0001 SEG0:14 15
0010 SEG0:16 17
0011 SEG0:18 19
0100 SEG0:20 21
0101 SEG0:22 23
0110 SEG0:23 24
0111 SEG0:24 25
1000 SEG0:26 27