Datasheet

225
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0 compared to none
addressed COM lines. Non-energized segments are in phase with the addressed COM0, and energized segments
have opposite phase and large amplitude. For waveform figures refer to ”Mode of operation” on page 226. Latched
data from LCDDR4 - LCDDR0 is multiplexed into the decoder. The decoder is controlled from the LCD timing and
sets up signals controlling the analog switches to produce an output waveform. Next, COM1 is addressed, and
latched data from LCDDR9 - LCDDR5 is input to decoder. Addressing continuous until all COM lines are
addressed according to number of common (duty). The display data are latched before a new frame start.
24.2.5 LCD Contrast Controller/Power Supply
The peak value (V
LCD
) on the output waveform determines the LCD Contrast. V
LCD
is controlled by software from
2.6V to 3.35V independent of V
CC
. An internal signal inhibits output to the LCD until V
LCD
has reached its target
value.
24.2.6 LCDCAP
An external capacitor (typical >470nF) must be connected to the LCDCAP pin as shown in Figure 24-2, if the LCD
module is enabled and configured to use internal power. This capacitor acts as a reservoir for LCD power (V
LCD
). A
large capacitance reduces ripple on V
LCD
but increases the time until V
LCD
reaches its target value.
Figure 24-2. LCDCAP connection.
24.2.7 LCD Buffer Driver
Intermediate voltage levels are generated from buffers/drivers. The buffers are active the amount of time specified
by LCDDC[2:0] in LCDCCR. Then LCD output pins are tri-stated and buffers are switched off. Shortening the drive
time will reduce power consumption, but displays with high internal resistance or capacitance may need longer
drive time to achieve sufficient contrast.
24.2.8 Display requirements
When using more than one common pin, the maximum period the LCD drivers can be turned on for each voltage
transition on the LCD pins is 50% of the prescaled LCD clock period, clk
LCD_PS
. To avoid flickering, it is recom-
mended to keep the framerate above 30Hz, thus giving a maximum drive time of approximately 2ms when using
1/2 or 1/4 duty, and approximately 2.7ms when using 1/3 duty. To achieve satisfactory contrast, all segments on
the LCD display must therefore be able to be fully charged/discharged within 2 or 2.7ms, depending on the number
of common pins.
24.2.9 Minimizing power consumption
By keeping the percentage of the time the LCD drivers are turned on at a minimum, the power consumption of the
LCD driver can be minimized. This can be achieved by using the lowest acceptable frame rate, and using low
power waveform if possible. The drive time should be kept at the lowest setting that achieves satisfactory contrast
for a particular display, while allowing some headroom for production variations between individual LCD drivers
and displays. Note that some of the highest LCD voltage settings may result in high power consumption when V
CC
is below 2.0V. The recommended maximum LCD voltage is 2×(V
CC
- 0.2V).
321
64
63
62
LCDCAP