Datasheet

205

ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]

8284E–AVR–02/2013

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is

activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog

Comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making

the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt.

When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To

make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings

are shown in Table 22-2 on page 205.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt

Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.

22.3.3 DIDR1 – Digital Input Disable Register 1

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written to logic one, the digital input buffer on the AIN1/0 pin disabled. The corresponding PIN Reg-

ister bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the

digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the dig-

ital input buffer.

Table 22-2. ACIS1/ACIS0 settings.

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

01Reserved

1 0 Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

Bit 76543210

(0x7F)

– – – – – – AIN1D AIN0D DIDR1

Read/Write RRRRRRR/WR/W

Initial Value00000000