Datasheet

200
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
21.5.2 USISR – USI Status Register
The Status Register contains Interrupt Flags, line Status Flags and the counter value.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is detected. When output
disable mode or Three-wire mode is selected, the flag is set when the 4-bit counter is incremented.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global Interrupt Enable
Flag are set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the
start detection hold of USCL in Two-wire mode. A start condition interrupt will wake up the processor from all sleep
modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An interrupt will be gen-
erated when the flag is set while the USIOIE bit in USICR and the Global Interrupt Enable Flag are set. The flag will
only be cleared if a one is written to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in
Two-wire mode. A counter overflow interrupt will wake up the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is
cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing
Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag is only valid when
Two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration.
• Bits 3:0 – USICNT[3:0]: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the
CPU.
The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a
Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of
the setting of the USICS[1:0] bits. For external clock operation a special feature is added that allows the clock to be
generated by writing to the USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting
an external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM[1:0] = 0) the external clock input (USCK/SCL) are can still
be used by the counter.
21.5.3 USICR – USI Control Register
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe.
Bit 76543 210
(0xB9)
USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 USISR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
(0xB8) USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR
Read/Write R/W R/W R/W R/W R/W R/W W W
Initial Value 0 0 0 0 0 0 0 0