Datasheet

192
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn
bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).
20.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers n
• Bit 15:12 – Reserved
These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when
UBRRnH is written.
• Bit 11:0 – UBRR[11:0]: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four most significant bits,
and the UBRRnL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the
Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate
update of the baud rate prescaler.
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1119-bit
Figure 20-12. UCPOLn bit settings.
UCPOLn
Transmitted data changed (output
of TxD pin)
Received data sampled (input on
RxD pin)
0 Rising XCK Edge Falling XCK Edge
1 Falling XCK Edge Rising XCK Edge
Figure 20-11. UCSZ bits settings. (Continued)
UCSZn2 UCSZn1 UCSZn0 Character size
Bit 151413121110 9 8
– – – – UBRRn[11:8] UBRRnH
UBRRn[7:0] UBRRnL
76543210
Read/WriteRRRRR/WR/WR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000