Datasheet

190
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
unaffected by the MPCMn setting. For more detailed information see ”Multi-processor Communication Mode” on
page 184.
20.11.3 UCSRnB – USART Control and Status Register n B
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt will be generated
only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in
UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated
only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCS-
RnA is set.
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only
if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCS-
RnA is set.
• Bit 4 – RXEN0: Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxD
pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn
Flags.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the
TxD pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until
ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Reg-
ister do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD port.
• Bit 2 – UCSZn2: Character Size
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe) in a
frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be
read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits.
Must be written before writing the low bits to UDRn.
Bit 76543210
RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n UCSRnB
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0