Datasheet

168
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
20. USART0
20.1 Features
• Full duplex operation (independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous operation
• Master or Slave Clocked Synchronous operation
• High resolution baud rate generator
• Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data overrun detection
• Framing error detection
• Noise filtering includes false Start Bit detection and Digital Low Pass filter
• Three separate interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication mode
• Double Speed Asynchronous Communication mode
20.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial
communication device.
A simplified block diagram of the USART Transmitter is shown in Figure 20-1 on page 169. CPU accessible I/O
Registers and I/O pins are shown in bold.
The Power Reduction USART bit, PRUSART0, in ”PRR – Power Reduction Register” on page 45 must be written
to zero to enable USART0 module.