Datasheet

158

ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]

8284E–AVR–02/2013

19. SPI – Serial Peripheral Interface

19.1 Features

• Full-duplex, three-wire Synchronous Data Transfer

• Master or Slave operation

• LSB First or MSB First Data Transfer

• Seven programmable bit rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle mode

• Double Speed (CK/2) Master SPI mode

19.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P and peripheral devices or between

several AVR devices. A simplified block diagram of the Serial Peripheral Interface is shown in Figure 19-1 on page

158.

The PRSPI bit in ”PRR – Power Reduction Register” on page 45 must be written to zero to enable the SPI module.

Figure 19-1. SPI block diagram

(1)

Note: 1. Refer to ”Pin configurations” on page 2, and Table 14-6 on page 74 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2 on page 159. The system

consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle

SPI2X

DIVIDER

/2/4/8/16/32/64/128