Datasheet

156
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has
been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates
that TCCR2A is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated
value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When reading TCNT2, the actual timer
value is read. When reading OCR2A or TCCR2A, the value in the temporary storage register is read.
18.10.5 TIMSK2 – Timer/Counter2
Interrupt Mask Register
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Com-
pare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2
occurs, that is, when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, that is, when
the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2.
18.10.6 TIFR2 – Timer/Counter2 Interrupt Flag Register
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A –
Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A
(Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match
Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes count-
ing direction at 0x00.
Bit 76543210
(0x70)
– – – – – – OCIE2A TOIE2 TIMSK2
Read/Write RRRRRRR/WR/W
Initial Value00000000
Bit 76543210
0x17 (0x37)
– – – – – – OCF2A TOV2 TIFR2
Read/Write RRRRRRR/WR/W
Initial Value00000000