Datasheet

150
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Figure 18-9. Timer/Counter timing diagram, with prescaler (f
clk_I/O
/8).
Figure 18-10 shows the setting of OCF2A in all modes except CTC mode.
Figure 18-10. Timer/Counter timing diagram, setting of OCF2A, with prescaler (f
clk_I/O
/8).
Figure 18-11 on page 150 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
Figure 18-11. Timer/Counter timing diagram, Clear Timer on Compare Match mode, with prescaler (f
clk_I/O
/8).
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)