Datasheet

145
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Figure 18-4. Compare Match Output Unit, schematic.
The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either
of the COM2A[1:0] bits are set. However, the OC2A pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2A pin (DDR_OC2A) must be
set as output before the OC2A value is visible on the pin. The port override function is independent of the Wave-
form Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled.
Note that some COM2A[1:0] bit settings are reserved for certain modes of operation. See ”Register Description” on
page 153.
18.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM2A[1:0] bits differently in normal, CTC, and PWM modes. For all modes,
setting the COM2A[1:0] = 0 tells the Waveform Generator that no action on the OC2A Register is to be performed
on the next compare match. For compare output actions in the non-PWM modes refer to Table 18-3 on page 153.
For fast PWM mode, refer to Table 18-4 on page 154, and for phase correct PWM refer to Table 18-5 on page 154.
A change of the COM2A[1:0] bits state will have effect at the first compare match after the bits are written. For non-
PWM modes, the action can be forced to have immediate effect by using the FOC2A strobe bits.
18.7 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM2[1:0]) and Compare Output mode (COM2A[1:0]) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM2A[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-
inverted PWM). For non-PWM modes the COM2A[1:0] bits control whether the output should be set, cleared, or
toggled at a compare match (See Section “18.6” on page 144.).
For detailed timing information refer to ”Timer/Counter timing diagrams” on page 149.
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA B U S
FOCnx
clk
I/O