Datasheet

140
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when
the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
17.4.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0A –
Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the Timer/Counter0 Compare match
Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0
changes counting direction at 0x00.
17.4.6 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is writ-
ten to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This
ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the
risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits
are cleared by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the
same prescaler and a reset of this prescaler will affect both timers.
Bit 76543210
0x15 (0x35)
– – – – – –OCF0ATOV0 TIFR0
Read/Write RRRRRRR/WR/W
Initial Value00000000
Bit 7 6 5 4 3 2 1 0
0x23 (0x43) TSM
– – – – – PSR2 PSR10 GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0