Datasheet

137
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
17.4 Register description
17.4.1 TCCR0A – Timer/Counter Control Register A
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibil-
ity with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When
writing a logical one to the FOC0A bit, an immediate compare match is forced on the Waveform Generation unit.
The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and
what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal
mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See
Table 17-1 and ”Modes of Operation” on page 100.
Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the function-
ality and location of these bits are compatible with previous versions of the timer.
• Bit 5:4 – COM0A1:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the
OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting.
Table 17-2 on page 138 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC
mode (non-PWM).
Bit 76 5 4 3210
0x24 (0x44)
FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 TCCR0A
Read/Write W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 17-1. Waveform Generation mode bit description
(1)
.
Mode
WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter mode
of operation TOP
Update of
OCR0A at
TOV0 Flag Set
on
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR0A Immediate MAX
3 1 1 Fast PWM 0xFF BOTTOM MAX