Datasheet

108
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow
interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when
the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
15.9.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0A –
Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the Timer/Counter0 Compare match
Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0
changes counting direction at 0x00.
Bit 76543210
0x15 (0x35)
– – – – – –OCF0ATOV0 TIFR0
Read/Write RRRRRRR/WR/W
Initial Value00000000