Datasheet

103
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the coun-
ter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count
direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase cor-
rect PWM mode is shown on Figure 15-7. The TCNT0 value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small hor-
izontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.
Figure 15-7. Phase correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the
COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM0A1:0 to three (See Table 18-5 on page 154). The actual OC0A value will only be visible on the port pin if the
data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0A
Register at the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clear-
ing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter decrements. The PWM
frequency for the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 15-7 OCn has a transition from high to low even though there is no Compare
Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a
transition without Compare Match.
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCn
OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Update
f
OCnxPCPWM
f
clk_I/O
N 510
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