Datasheet

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ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active
in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock
cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a
timed sequence.
10.11.3 PRR – Power Reduction Register
• Bit 7:5 - Reserved
These bits are reserved and will always read as zero.
• Bit 4 - PRLCD: Power Reduction LCD
Writing logic one to this bit shuts down the LCD controller. The LCD controller must be disabled and the display
discharged before shut down. See ”Disabling the LCD” on page 231 for details on how to disable the LCD
controller.
• Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, opera-
tion will continue like before the shutdown.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When
waking up the SPI again, the SPI should be re initialized to ensure proper operation.
• Bit 1 - PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the
USART again, the USART should be re initialized to ensure proper operation.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog com-
parator cannot use the ADC input MUX when the ADC is shut down.
Note: The Analog Comparator is disabled using the ACD-bit in the ”ACSR – Analog Comparator Control and Status Register”
on page 204.
Bit 7 6 5 4 3 2 1 0
(0x64)
– – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC PRR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0