Datasheet

36
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster
than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were
readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock fre-
quency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2
is the period corresponding to the new prescaler setting.