Datasheet

315

ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]

8284E–AVR–02/2013

28.9.7 Data Registers

The Data Registers are selected by the JTAG instruction registers described in section ”Programming Specific

JTAG Instructions” on page 312. The Data Registers relevant for programming operations are:

• Reset Register

• Programming Enable Register

• Programming Command Register

• Flash Data Byte Register

28.9.8 Reset Register

The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the

part before entering Programming mode.

A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there

is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will

remain reset for a Reset Time-out period (refer to ”Clock sources” on page 30) after releasing the Reset Register.

The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 26-1

on page 247.

28.9.9 Programming Enable Register

The Programming Enable Register is a 16-bit register. The contents of this register is compared to the program-

ming enable signature, binary code 0b1010_0011_0111_0000. When the contents of the register is equal to the

programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on

Reset, and should always be reset when leaving Programming mode.

Figure 28-14. Programming Enable register.

28.9.10 Programming Command Register

The Programming Command Register is a 15-bit register. This register is used to serially shift in programming

commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction

Set is shown in Table 28-17 on page 317. The state sequence when shifting in the programming commands is

illustrated in Figure 28-16 on page 320.

TDI

TDO

ClockDR & PROG_ENABLE

Programming Enable

0xA370