Datasheet

308
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Figure 28-10. Serial programming and verify
(1)
.
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.
2. V
CC
- 0.3V < AVCC < V
CC
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the
Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation
turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
>= 12MHz
High: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
>= 12MHz
28.8.2 Serial Programming Algorithm
When writing serial data to the Atmel
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P, data is clocked on the rising edge of
SCK.
When reading data from the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P, data is clocked on the falling edge of
SCK. See Figure 28-11 for timing details.
To program and verify the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P in the serial programming mode, the
following sequence is recommended (See four byte instruction formats in Table 28-16):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some systems, the program-
mer can not guarantee that SCK is held low during power-up. In this case, RESET
must be given a positive
pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction
to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchronization. When in
sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruc-
tion. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did
not echo back, give RESET
a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The page size is found in Table 28-7 on page 296. The mem-
ory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the
Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be
loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
+1.8 - 5.5V
AVCC
+1.8 - 5.5V
(2)