Datasheet

307
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Notes: 1. t
WLRH
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
2. t
WLRH_CE
is valid for the Chip Erase command.
28.8 Serial downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled
to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET
is set low, the
Programming Enable instruction needs to be executed first before program/erase operations can be executed.
NOTE, in Table 28-14 on page 307, the pin mapping for SPI programming is listed. Not all parts use the SPI pins
dedicated for the internal SPI interface.
28.8.1 Serial programming pin mapping
t
BVPH
BS1 Valid before PAGEL High 67
ns
t
PHPL
PAGEL Pulse Width High 150
t
PLBX
BS1 Hold after PAGEL Low 67
t
WLBX
BS2/1 Hold after WR Low 67
t
PLWL
PAGEL Low to WR Low 67
t
BVWL
BS1 Valid to WR Low 67
t
WLWH
WR Pulse Width Low 150
t
WLRL
WR Low to RDY/BSY Low 0 1 s
t
WLRH
WR Low to RDY/BSY High
(1)
3.7 4.5
ms
t
WLRH_CE
WR Low to RDY/BSY High for Chip Erase
(2)
7.5 9
t
XLOL
XTAL1 Low to OE Low 0
ns
t
BVDV
BS1 Valid to DATA valid 0 250
t
OLDV
OE Low to DATA Valid 250
t
OHDZ
OE High to DATA Tri-stated 250
Table 28-13. Parallel programming characteristics, V
CC
= 5V ±10%. (Continued)
Symbol Parameter Min. Typ. Max. Units
Table 28-14. Pin mapping serial programming.
Symbol Pins I/O Description
MOSI PB2 I Serial Data in
MISO PB3 O Serial Data out
SCK PB1 I Serial Clock