Datasheet

306
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Figure 28-8. Parallel programming timing, loading sequence with timing requirements
(1)
.
Note: 1. The timing requirements shown in Figure 28-7 (that is, t
DVXH
, t
XHXL
, and t
XLDX
) also apply to loading operation.
Figure 28-9. Parallel programming timing, reading sequence (within the same page) with timing requirements
(1)
.
Note: 1. The timing requirements shown in Figure 28-7 on page 305 (that is, t
DVXH
, t
XHXL
, and t
XLDX
) also apply to reading
operation.
Table 28-13. Parallel programming characteristics, V
CC
= 5V ±10%.
Symbol Parameter Min. Typ. Max. Units
V
PP
Programming Enable Voltage 11.5 12.5 V
I
PP
Programming Enable Current 250 A
t
DVXH
Data and Control Valid before XTAL1 High 67
ns
t
XLXH
XTAL1 Low to XTAL1 High 200
t
XHXL
XTAL1 Pulse Width High 150
t
XLDX
Data and Control Hold after XTAL1 Low 67
t
XLWL
XTAL1 Low to WR Low 0
t
XLPH
XTAL1 Low to PAGEL high 0
t
PLXH
PAGEL low to XTAL1 high 150
XTAL1
PAGEL
t
PLXH
XLXH
t
t
XLPH
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ