Datasheet
251
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Figure 26-5 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal
is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an observe-only
cell. In addition to the main clock, the timer Oscillator is scanned in the same way. The output from the internal RC
Oscillator is not scanned, as this Oscillator does not have external connections.
Figure 26-5. Boundary-scan cells for oscillators and clock options.
Table 26-2 summaries the scan registers for the external clock pin XTAL1, oscillators with XTAL1/XTAL2 connec-
tions as well as 32kHz Timer Oscillator.
Notes: 1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the internal Oscilla-
tor and the JTAG TCK clock. If possible, scanning an external clock is preferred.
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock configuration is con-
sidered fixed for a given application. The user is advised to scan the same clock option as to be used in the final
system. The enable signals are supported in the scan chain because the system logic can disable clock options in
sleep modes, thereby disconnecting the Oscillator pins from the scan path if not provided.
26.5.4 Scanning the Analog Comparator
The relevant Comparator signals regarding Boundary-scan are shown in Figure 26-6. The Boundary-scan cell from
Figure 26-7 is attached to each of these signals. The signals are described in Table 26-3 on page 253.
The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital
port pin as well.
Table 26-2. Scan signals for the oscillator
(1)(2)(3)
.
Enable signal Scanned clock line Clock option
Scanned clock line
when not used
EXTCLKEN EXTCLK (XTAL1) External Clock 0
OSCON OSCCK
External XTAL
External Ceramic Resonator
1
OSC32EN OSC32CK Low Freq. External XTAL 1
0
1
DQ
From
Previous
Cell
ClockDR
ShiftDR
To
Next
Cell
To System Logic
FF1
0
1
DQ DQ
G
0
1
From
Previous
Cell
ClockDR UpdateDR
ShiftDR
To
Next
Cell EXTEST
From Digital Logic
XTAL1/TOSC1 XTAL2/TOSC2
Oscillator
ENABLE OUTPUT