Datasheet

250
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Figure 26-3. General Port Pin, schematic diagram.
26.5.2 Scanning the RESET pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage
Parallel programming. An observe-only cell as shown in Figure 26-4 is inserted both for the 5V reset signal; RSTT,
and the 12V reset signal; RSTHV.
Figure 26-4. Observe-only cell.
26.5.3 Scanning the Clock pins
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock,
(High Frequency) XTAL Oscillator, Low-frequency XTAL Oscillator, and Ceramic Resonator.
CLK
RPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
WPx: WRITE PINx REGISTER
PUD: PULLUP DISABLE
CLK : I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
Q
Q
D
Q
Q
D
CLR
DDxn
PINxn
DATA BU S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
I/O
See Boundary-scan
Description for Details!
PUExn
OCxn
ODxn
IDxn
PUExn: PULLUP ENABLE for pin Pxn
OCxn: OUTPUT CONTROL for pin Pxn
ODxn: OUTPUT DATA to pin Pxn
IDxn: INPUT DATA from pin Pxn
RPx: READ PORTx PIN
RRx
RESET
Q
Q
D
CLR
PORTxn
WPx
0
1
WRx
0
1
DQ
From
Previous
Cell
ClockDR
ShiftDR
To
Next
Cell
From System Pin
To System Logic
FF1