Datasheet

240
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in
reset. When programmed and the JTD bit in MCUCR is cleared, the TAP pins are internally pulled high and the
JTAG is enabled for Boundary-scan and programming. The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET
pin is monitored by the debug-
ger to be able to detect external reset sources. The debugger can also pull the RESET
pin low to reset the whole
system, assuming only open collectors on the reset line are used in the application.
Figure 25-1. Block diagram.
TAP
CONTROLLER
TDI
TDO
TCK
TMS
FLASH
MEMORY
AVR CPU
DIGITAL
PERIPHERAL
UNITS
JTAG / AVR CORE
COMMUNICATION
INTERFACE
BREAKPOINT
UNIT
FLOW CONTROL
UNIT
OCD STATUS
AND CONTROL
INTERNAL
SCAN
CHAIN
M
U
X
INSTRUCTION
REGISTER
ID
REGISTER
BYPASS
REGISTER
JTAG PROGRAMMING
INTERFACE
PC
Instruction
Address
Data
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
ANALOG
PERIPHERIAL
UNITS
I/O PORT 0
I/O PORT n
BOUNDARY SCAN CHAIN
Analog inputs
Control & Clock lines
DEVICE BOUNDARY