Datasheet

237
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
resistance may need longer drive time to achieve satisfactory contrast. Note that the drive time will never be longer
than one half prescaled LCD clock period, even if the selected drive time is longer. When using static duty or blank-
ing, drive time will always be one half prescaled LCD clock period.
New values take effect immediately, and can cause small glitches in the display output. This can be avoided by
setting the LCDBL in LCDCRA, and wait to the next start of frame before changing LCDDC[2:0].
Note: The drive time will be longer dependent on oscillator startup time.
• Bit 4 – LCDMDT: LCD Maximum Drive Time
Writing this bit to one turns the LCD drivers on 100% all the time, regardless of the drive time configured by
LCDDC[2:0].
• Bits 3:0 – LCDCC[3:0]: LCD Contrast Control
The LCDCC[3:0] bits determine the maximum voltage V
LCD
on segment and common pins. The different selections
are shown in Table 24-8. New values take effect every beginning of a new frame.
Table 24-7. LCD display configuration.
LCDDC2 LCDDC1 LCDDC0 Nominal drive time
0 0 0 300µs
0 0 1 70µs
0 1 0 150µs
0 1 1 450µs
1 0 0 575µs
1 0 1 850µs
1 1 0 1150µs
1 1 1 50% of clk
LCD_PS
Table 24-8. LCD contrast control.
LCDCC3 LCDCC2 LCDCC1 LCDCC0 Maximum voltage V
LCD
0000 2.60
0001 2.65
0010 2.70
0011 2.75
0100 2.80
0101 2.85
0110 2.90
0111 2.95
1000 3.00
1001 3.05
1010 3.10
1011 3.15
1100 3.20