Datasheet

222
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
23.9.5 DIDR0 – Digital Input Disable Register 0
• Bit 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the
ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power
consumption in the digital input buffer.
Table 23-7. ADC auto trigger source selections.
ADTS2 ADTS1 ADTS0 Trigger source
0 0 0 Free Running mode
0 0 1 Analog Comparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare MatchA
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event
Bit 76543210
(0x7E) ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000