Datasheet

206
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero w hen this bit i s set. When an analog si gnal is appli ed to the AIN1 /0 pin and the digital inpu t from this pin is not needed, this bit s hould be wr itten logic one to reduce power consumpti on in the di gital input bu ffer.
23. Analog to Digital Converter
23.1 Features
10-bit resolution
0.5LSB integral non-linearity
±2LSB absolute accuracy
13µs - 260µs conversion time (50kHz to 1MHz ADC clock)
Up to 15kSPS at maximum resolution (200kHz ADC clock)
Eight multiplexed single ended input channels
Optional left adjustment for ADC result readout
0 - V
CC
ADC input voltage range
Selectable 1.1V ADC reference voltage
Free running or Single Conversion mode
ADC start conversion by auto triggering on interrupt sources
Interrupt on ADC conversion complete
Sleep Mmode noise canceler
23.2 Overview
The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P features a 10-bit succes-
sive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows eight single-
ended voltage inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant
level during conversion. A block diagram of the ADC is shown in Figure 23-1 on page 207.
The ADC has a separate analog supply voltage pin, AVCC. AV
CC
must not differ more than ±0.3V from V
CC
. See
the paragraph ”ADC Noise Canceler” on page 212 on how to connect this pin.
Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage reference may be exter-
nally decoupled at the AREF pin by a capacitor for better noise performance.
The PRADC, in ”PRR – Power Reduction Register” on page 45 must be written to zero to enable the ADC module.