Datasheet

202
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
• Bit 3:2 – USICS[1:0]: Clock Source Select
These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is
changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source
(USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is
transparent and therefore the output is changed immediately. Clearing the USICS1:0 bits enables software strobe
option. When using this option, writing a one to the USICLK bit clocks both the Shift Register and the counter. For
external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external
clocking and software clocking by the USITC strobe bit.
Table 21-2 shows the relationship between the USICS1:0 and USICLK setting and clock source used for the Shift
Register and the 4-bit counter.
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the counter to increment by one,
provided that the USICS[1:0] bits are set to zero and by doing so the software clock strobe option is selected. The
output will change immediately when the clock strobe is executed, i.e., in the same instruction cycle. The value
shifted into the Shift Register is sampled the previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a
Clock Select Register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-
bit counter (see Table 21-2 on page 202).
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0. The toggling is inde-
pendent of the setting in the Data Direction Register, but if the PORT value is to be shown on the pin the DDRE4
must be set as output (to one). This feature allows easy clock generation when implementing master devices. The
bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC
strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when oper-
ating as a master device.
Table 21-2. Relations between the USICS1:0 and USICLK Setting
USICS1 USICS0 USICLK Shift Register Clock Source 4-bit Counter Clock Source
0 0 0 No Clock No Clock
001
Software clock strobe
(USICLK)
Software clock strobe
(USICLK)
01X
Timer/Counter0 Compare
Match
Timer/Counter0 Compare
Match
1 0 0 External, positive edge External, both edges
1 1 0 External, negative edge External, both edges
1 0 1 External, positive edge Software clock strobe (USITC)
1 1 1 External, negative edge Software clock strobe (USITC)