Datasheet

199
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
21.4 Alternative USI Usage
When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible
design.
21.4.1 Half-duplex Asynchronous Data Transfer
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher perfor-
mance UART than by software only.
21.4.2 4-bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked
externally, both clock edges will generate an increment.
21.4.3 12-bit Timer/Counter
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit counter.
21.4.4 Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag
and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit.
21.4.5 Software Interrupt
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
21.5 Register description
21.5.1 USIDR – USI Data Register
The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register (USIDR) the Serial Regis-
ter is accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the
value written and no shift is performed. A (left) shift operation is performed depending of the USICS1...0 bits set-
ting. The shift operation can be controlled by an external clock edge, by a Timer/Counter0 Compare Match, or
directly by software using the USICLK strobe bit. Note that even when no wire mode is selected (USIWM1...0 = 0)
both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the Shift
Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch to the most signif-
icant bit (bit 7) of the Data Register. The output latch is open (transparent) during the first half of a serial clock cycle
when an external clock source is selected (USICS1 = 1), and constantly open when an internal clock source is
used (USICS1 = 0). The output will be changed immediately when a new MSB written as long as the latch is open.
The latch ensures that data input is sampled and data output is changed on opposite clock edges.
Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the
Shift Register.
Bit 7 6 5 4 3 2 1 0
(0xBA) MSB LSB USIDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0