Datasheet

194
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK
pin, Timer/Counter0 Compare Match or from software.
The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It
can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter
overflows.
21.3 Functional descriptions
21.3.1 Three-wire Mode
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the
slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names
used by this mode are: DI, DO, and USCK.
Figure 21-2. Three-wire mode operation, simplified diagram.
Figure 21-2 on page 194 shows two USI units operating in Three-wire mode, one as Master and one as Slave. The
two Shift Registers are interconnected in such way that after eight USCK clocks, the data in each register are inter-
changed. The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or
USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master
device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.
Figure 21-3. Three-wire mode, timing diagram.
SLAVE
MASTER
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
PORTxn
MSB
MSB
654321LSB
1 2 3 4 5 6 7 8
654321LSB
USCK
USCK
DO
DI
DCBA E
CYCLE
( Reference )