Datasheet

191
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
20.11.4 UCSRnC – USART Control and Status Register n C
• Bit 6 – UMSELn: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically gener-
ate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for
the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn Flag in UCSRnA will
be set.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a
frame the Receiver and Transmitter use.
Bit 7 6 543 2 1 0
– UMSELn UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
Figure 20-8. UMSELn bit settings.
UMSELn Mode
0 Asynchronous operation
1 Synchronous operation
Figure 20-9. UPMn bits settings.
UPMn1 UPMn0 Parity mode
0 0 Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Figure 20-10. USBSn bit settings.
USBSn Stop bit(s)
01-bit
12-bit
Figure 20-11. UCSZ bits settings.
UCSZn2 UCSZn1 UCSZn0 Character size
0005-bit
0016-bit
0107-bit
0118-bit