Datasheet

172
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
20.3.3 External Clock
External clocking is used by the synchronous slave modes of operation. The description in this section refers to
Figure 20-2 on page 170 for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-sta-
bility. The output from the synchronization register must then pass through an edge detector before it can be used
by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maxi-
mum external XCK clock frequency is limited by the following equation:
Note that f
osc
depends on the stability of the system clock source. It is therefore recommended to add some margin
to avoid possible loss of data due to frequency variations.
20.3.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock
output (Master). The dependency between the clock edges and data sampling or data change is the same. The
basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output
(TxD) is changed.
Figure 20-3. Synchronous mode XCK timing.
The UCPOLn bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data
change. As Figure 20-3 shows, when UCPOLn is zero the data will be changed at rising XCK edge and sampled at
falling XCK edge. If UCPOLn is set, the data will be changed at falling XCK edge and sampled at rising XCK edge.
20.4 Frame formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and option-
ally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8 or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of
nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,
before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the com-
f
XCK
f
OSC
4
-----------

RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample