Datasheet
171
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Signal description:
txclk Transmitter clock (Internal Signal).
rxclk Receiver base clock (Internal Signal).
xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
fosc XTAL pin frequency (System Clock).
20.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The
description in this section refers to Figure 20-2.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable pres-
caler or baud rate generator. The down-counter, running at system clock (f
osc
), is loaded with the UBRRn value
each time the counter has counted down to zero or when the UBRRnL Register is written. A clock is generated
each time the counter reaches zero. This clock is the baud rate generator clock output (= f
osc
/(UBRRn+1)). The
Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate genera-
tor output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state
machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCK bits.
Table 20-1 on page 171 contains equations for calculating the baud rate (in bits per second) and for calculating the
UBRRn value for each mode of operation using an internally generated clock source.
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).
BAUD Baud rate (in bits per second, bps).
f
OSC
System Oscillator clock frequency.
UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095).
Some examples of UBRRn values for some system clock frequencies are found in Table 20-4 on page 185.
20.3.2 Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has effect for the asyn-
chronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for
asynchronous communication. Note however that the Receiver will in this case only use half the number of sam-
ples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting
and system clock are required when this mode is used. For the Transmitter, there are no downsides.
Table 20-1. Equations for Calculating Baud Rate Register Setting
Operating mode Equation for calculating baud rate
(1)
Equation for calculating UBRRn value
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode
(U2Xn = 1)
Synchronous Master
mode
BAUD
f
OSC
16 UBRRn 1+
------------------------------------------=
UBRRn
f
OSC
16BAUD
----------------------- - 1–=
BAUD
f
OSC
8 UBRRn 1+
-------------------------------------- -=
UBRRn
f
OSC
8BAUD
-------------------- 1–=
BAUD
f
OSC
2 UBRRn 1+
-------------------------------------- -=
UBRRn
f
OSC
2BAUD
-------------------- 1–=