Datasheet

154
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Table 18-4 shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored,
but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on page 147 for more details.
Table 18-5 shows the COM2[1:0] bit functionality when the WGM2[1:0] bits are set to phase correct PWM mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored,
but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on page 148 for more details.
• Bit 2:0 – CS2[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 18-6 on page 154.
0 1 Toggle OC2A on compare match.
1 0 Clear OC2A on compare match.
1 1 Set OC2A on compare match.
Table 18-4. Compare Output mode, fast PWM mode
(1)
.
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected
01Reserved
10
Clear OC2A on compare match, set OC2A at BOTTOM
(non-inverting mode)
11
Set OC2A on compare match, clear OC2A at BOTTOM
(inverting mode)
Table 18-5. Compare Output mode, phase correct PWM mode
(1)
.
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected
01Reserved
10
Clear OC2A on compare match when up-counting. Set OC2A on
compare match when counting down
11
Set OC2A on compare match when up-counting. Clear OC2A on
compare match when counting down
Table 18-6. Clock Select bit description.
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
001clk
T2S
/(No prescaling)
010clk
T2S
/8 (From prescaler)
011clk
T2S
/32 (From prescaler)
100clk
T2S
/64 (From prescaler)
101clk
T2S
/128 (From prescaler)
110clk
T
2
S
/256 (From prescaler)
111clk
T
2
S
/1024 (From prescaler)
Table 18-3. Compare Output mode, non-PWM mode. (Continued)
COM2A1 COM2A0 Description