Datasheet

148
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM2A[1:0] bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2A to toggle
its logical level on each compare match (COM2A[1:0] = 1). The waveform generated will have a maximum fre-
quency of f
oc2
=f
clk_I/O
/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode,
except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
18.7.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM2[1:0] = 1) provides a high resolution phase correct PWM waveform genera-
tion option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from
BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC2A) is cleared on the compare match between TCNT2 and OCR2A while counting up, and set on the compare
match while counting down. In inverting Output Compare mode, the operation is inverted. The dual-slope operation
has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the coun-
ter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count
direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase cor-
rect PWM mode is shown on Figure 18-7. The TCNT2 value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small hor-
izontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2.
Figure 18-7. Phase Correct PWM Mode, timing diagram.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the
COM2A[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM2A[1:0] to three (See Table 18-5 on page 154). The actual OC2A value will only be visible on the port pin if the
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Update