Datasheet

141
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
18.1 Features
• Single Compare Unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, phase correct Pulse Width Modulator (PWM)
• Frequency generator
• 10-bit clock prescaler
• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)
• Allows clocking from external 32kHz watch XTAL independent of the I/O Clock
18.2 Overview
Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram
of the 8-bit Timer/Counter is shown in Figure 18-1. For the actual placement of I/O pins, refer to ”Pin configura-
tions” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-
specific I/O Register and bit locations are listed in the ”Register Description” on page 153.
Figure 18-1. 8-bit Timer/Counter block diagram.
18.2.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Interrupt request (shorten
as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually
masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins,
as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register
Timer/Counter
DATA B US
=
TCNTn
Waveform
Generation
OCnx
= 0
Control Logic
= 0xFF
TOPBOTTOM
count
clear
direction
TOVn
(Int.Req.)
OCnx
(Int.Req.)
Synchronization Unit
OCRnx
TCCRnx
ASSRn
Status flags
clk
I/O
clk
ASY
Synchronized Status flags
asynchronous mode
select (ASn)
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
Tn
clk
I/O