Datasheet

109
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
16. 16-bit Timer/Counter1
16.1 Features
• True 16-bit design (that is, allows 16-bit PWM)
• Two independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, phase correct Pulse Width Modulator (PWM)
• Variable PWM period
• Frequency generator
• External event counter
• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
16.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation,
and signal timing measurement.
Most register and bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number, and a lower case “x” replaces the Output Compare unit. However, when using the register
or bit defines in a program, the precise form must be used, that is, TCNT1 for accessing Timer/Counter1 counter
value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 16-1 on page 110. For the actual place-
ment of I/O pins, refer to ”Pin configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O
pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the ”Register description” on
page 128.
The PRTIM1 bit in ”PRR – Power Reduction Register” on page 45 must be written to zero to enable the
Timer/Counter1 module.