Datasheet

104
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
• OCR0A changes its value from MAX, like in Figure 15-7. When the OCR0A value is MAX the OCn pin value is the
same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at
MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.
15.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set. Figure 15-8 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 15-8. Timer/Counter timing diagram, no prescaling.
Figure 15-9 shows the same timing data, but with the prescaler enabled.
Figure 15-9. Timer/Counter timing diagram, with prescaler (f
clk_I/O
/8).
Figure 15-10 on page 104 shows the setting of OCF0A in all modes except CTC mode.
Figure 15-10. Timer/Counter timing diagram, setting of OCF0A, with prescaler (f
clk_I/O
/8).
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)