Atmel ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash DATASHEET Features • • • • • • • • • • • High performance, low power Atmel® AVR® 8-Bit Microcontroller Advanced RISC architecture – 130 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 16MIPS throughput at16MHz (Atmel ATmega169A/169PA/649A/649P) – Up to 20 MIPS throughput at 20MHz (Atmel ATmeg
1. Pin configurations Pinout - 64A (TQFP) and 64M1 (QFN/MLF) LCDCAP 1 (RXD/PCINT0) PE0 2 GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (COM0) PA1 (COM1) PA2 (COM2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout Atmel ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P. AVCC Figure 1-1. 64 1.
1.2 Pinout - 100A (TQFP) Figure 1-2. Pinout Atmel ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P.
Pinout - 64MC (DRQFN) Pinout Atmel ATmega169A/ATmega169PA. A4 A22 B4 B19 A21 A5 B5 B18 B6 A20 B17 A6 A7 A19 B16 A18 A34 B29 A33 B30 A31 B28 A32 B26 A30 B27 A3 B3 B20 A22 A4 B4 A5 B19 A21 B18 B5 A6 A20 B17 A19 B6 B16 B7 A7 A8 A18 A17 A16 B15 B8 A10 B9 A11 B10 A12 B11 A13 B12 A14 B13 A15 B14 A9 A2 A17 B15 B7 A8 B2 A23 A9 B3 A23 B20 B1 A10 B8 B21 B22 A24 B21 B10 A11 B9 B2 A3 A1 A25 A13 B11 A12 B22 A24 A16 B14 A15 A25 B1 A2 Table 1-1.
2. Overview The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a low-power CMOS 8-bit microcontroller based on the Atmel®AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block diagram GND Block diagram. PF0 - PF7 VCC PA0 - PA7 DATA DIR.
The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P provides the following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K bytes EEPROM, 1K/2K/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD controller with internal contrast control, three flexible Timer/Counters with compare modes, internal a
2.2 Comparison between Atmel ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P Table 2-1. Differences between: ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P.
2.3 Pin descriptions The following section describes the I/O-pin special functions. 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7...PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
Port E also serves the functions of various special features of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 80. 2.3.8 Port F (PF7...PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability.
2.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter. 2.3.17 LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Figure 24-2, if the LCD module is enabled and configured to use internal power.
3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device.
7. AVR CPU core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural overview Figure 7-1. Block diagram of the AVR architecture.
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
7.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
• One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU general purpose working registers. 7 0 Addr.
7.6 Stack pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
Figure 7-4. The parallel instruction fetches and instruction executions. T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-5. Single cycle ALU operation.
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags.
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
8. AVR memories This section describes the different memories in the Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P. The Atmel AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P features an EEPROM Memory for data storage. All three memory spaces are linear. 8.
instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 1280 (Atmel ATmega169A/169PA) and 2304/4352 (Atmel ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P) data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM.
Figure 8-3. On-chip data SRAM access cycles. T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 8.3 Next Instruction EEPROM data memory The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P contains 512/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ”Boot Loader Support – Read-While-Write Self-Programming” on page 278 for details about Boot programming.
Assembly code example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C code example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
Assembly code example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C code example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
8.4 I/O memory The I/O space definition of the Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is shown in ”Register summary” on page 871. All ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
8.6.
• Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM.
9. System clock and clock options 9.1 Clock systems and their distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power management and sleep modes” on page 39. The clock systems are detailed below. Figure 9-1. Clock distribution.
9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32kHz clock XTAL. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. It also allows the LCD controller output to continue while the rest of the device is in sleep mode. 9.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain.
This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9-3. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 29-12 on page 333.
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3...1 as shown in Table 9-5. Table 9-5. XTAL oscillator operating modes. CKSEL3..1 Frequency range [MHz] Recommended range for capacitors C1 and C2 for use with XTALs [pF] 100(1) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 Note: 1. This option should not be used with XTALs, only with ceramic resonators.
Table 9-7. Note: Maximum ESR recommendation for 32.768kHz watch XTAL Atmel ATmega169A/169PA. XTAL CL [pF] Maximum ESR [k] (1) 6.5 60 9 35 1. Maximum ESR is typical value based on characterization. The Low-frequency XTAL Oscillator provides an internal load capacitance, see Table 9-9 on page 33 at each TOSC pin.
The Low-frequency XTAL Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111” as shown in Table 9-11 on page 34. Start-up times are determined by the SUT Fuses as shown in Table 9-10. Table 9-10. Start-up times for the low-frequency XTAL oscillator clock selection. SUT1..0 Additional delay from reset (VCC = 5.0V) 00 4CK 01 4CK + 4.1ms Slowly rising power 10 4CK + 65ms Stable frequency at start-up Fast rising power or BOD enabled 11 Reserved Table 9-11. 9.
Table 9-13. Start-up times for the external clock selection. SUT1..0 Start-up time from powerdown and power-save Additional delay from reset (VCC = 5.0V) 00 6CK 14CK 01 6CK 14CK + 4.1ms Fast rising power 10 6CK 14CK + 65ms Slowly rising power 11 Recommended usage BOD enabled Reserved When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active.
9.11 9.11.1 Register Description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions.
10. Power management and sleep modes 10.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 10.2 Sleep modes Figure 9-1 on page 29 presents the different clock systems in the Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60µs to ensure that the BOD is working correctly before the MCU continues executing code. BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see ”MCUCR – MCU Control Register” on page 44. Writing this bit to one turns off the BOD in relevant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active, i.e. BODS set to zero.
10.7 Power-save mode When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.
10.10 Minimizing power consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 10.10.
10.10.6 Port pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
10.11 Register description 10.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 10-2. Table 10-2. Note: Sleep Mode Select.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. • Bit 5 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 10.11.
11. System control and reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 11-1. Reset logic. DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and reset characteristics” on page 334.
Figure 11-3. MCU start-up, RESET extended externally. VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and reset characteristics” on page 334) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
11.2.3 Brown-out detection The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
11.3 Internal voltage reference The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.3.1 Voltage reference enable signals and start-up time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in ”System and reset characteristics” on page 334.
Figure 11-7. Watchdog Timer. WATCHDOG OSCILLATOR 11.4.1 Timed sequences for changing the configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 11.4.2 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.
11.5 11.5.1 Register description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – – – JTRF WDRF BORF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 MCUSR See Bit Description • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. ”Timed sequences for changing the configuration of the Watchdog Timer” on page 51.
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (for example, by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
12. Interrupts 12.1 Overview This section describes the specifics of the interrupt handling as performed in the Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P. For a general explanation of the AVR interrupt handling, refer to ”Reset and interrupt handling” on page 17. 12.2 Interrupt vectors Table 12-1. Reset and interrupt vectors. Vector No.
3. PCINT2 and PCINT3 are only present in the Atmel ATmega3290A/3290PA/6490A/6490P. Table 12-2 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 12-2.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments 0x0000 RESET: ldi 0x0001 out SPH,r16 r16,high(RAMEND); Main program start 0x0002 ldi r16,low(RAMEND) 0x0003 0x0004 out sei SPL,r16 0x0005 xxx ; Set Stack Pointer to top of RAM ; Enable interrupts ; .
12.2.1 0x3831/0x7831 0x3832/0x7832 out sei SPL,r16 0x3833/0x7833 xxx ; Enable interrupts Moving interrupts between application and boot space he General Interrupt Control Register controls the placement of the Interrupt Vector table, see ”MCUCR – MCU Control Register” on page 59. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b.
12.3 12.3.1 Register description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS (1) BODSE (1) PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the Atmel ATmega169PA/329PA/3290PA/649P/6490P picoPower devices. • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
13. External interrupts 13.1 Overview The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins (2). Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15:8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7:0 pin toggles.
13.2 Pin change interrupt timing An example of timing of a pin change interrupt is shown in Figure 13-1. Figure 13-1. Pin change interrupt. pin_lat PCINT(0) D pcint_in_(0) Q clk 0 pcint_setflag pcint_syn PCIF pin_sync LE x PCINT(0) in PCMSK(x) clk clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF 13.3 13.3.
Table 13-1. 13.3.2 Interrupt 0 sense control. ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.
13.3.3 EIFR – External Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 PCIF3 (1) PCIF2 (1) PCIF1 PCIF0 – – – INTF0 Read/Write R/W R/W R/W R/W R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x1C (0x3C) EIFR • Bit 7 – PCIF3: Pin Change Interrupt Flag 3 When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
13.3.4 PCMSK3 – Pin Change Mask Register 3 (1) Bit 7 6 5 4 3 2 1 0 (0x73) – PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK3 • Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30...24 Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
14. I/O-ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
14.2 Ports as general digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 14-2. General digital I/O (1). PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WPx RRx SLEEP SYNCHRONIZER D Q L Q D WRx RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 14.2.
14.2.3 Switching between input and output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 14-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 14-4. Synchronization when reading a software assigned pin value.
Assembly code example (1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
Alternate port functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 14-5 shows how the port pin control signals from the simplified Figure 14-2 on page 66 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 14-5. Alternate port functions (1).
Table 14-2. Signal name Generic description of overriding signals for alternate functions. Full name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
14.3.1 Alternate functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller. Table 14-3. Port pin Port A pins alternate functions.
Table 14-5. 14.3.2 Overriding signals for alternate functions in PA3:PA0.
• OC1A/PCINT13, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external interrupt source.
Table 14-7 and Table 14-8 relate the alternate functions of Port B to the overriding signals shown in Figure 14-5 on page 71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 14-7. Overriding signals for alternate functions in PB7:PB4.
14.3.3 Alternate functions of Port C The Port C has an alternate function as SEG for the LCD Controller. Table 14-9. Port pin Port C pins alternate functions (SEG refers to 100-pin/64-pin pinout).
Table 14-11. Overriding signals for alternate functions in PC3:PC0. 14.3.
Table 14-13. Overriding signals for alternate functions PD7:PD4.
14.3.5 Alternate functions of Port E The Port E pins with alternate functions are shown in Table 14-15. Table 14-15. Port E pins alternate functions.
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source. • TXD/PCINT1 – Port E, Bit 1 TXD0, UART0 Transmit pin. PCINT1, Pin Change Interrupt Source 1: The PE1 pin can serve as an external interrupt source. • RXD/PCINT0 – Port E, Bit 0 RXD, USART0 Receive pin. Receive Data (Data input pin for the USART0).
Table 14-17. Overriding signals for alternate functions in PE3:PE0.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5. TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine.
Table 14-20. Overriding signals for alternate functions in PF3:PF0. 14.3.7 Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Alternate Functions of Port G The alternate pin configuration is as follows: Table 14-21.
• SEG – Port G, Bit 2 SEG, LCD front plane 4/4. • SEG – Port G, Bit 1 SEG, Segment driver 17/13. • SEG – Port G, Bit 0 SEG, LCD front plane 18/14. Table 14-21 and Table 14-22 relates the alternate functions of Port G to the overriding signals shown in Figure 145 on page 71. Table 14-22. Overriding signals for alternate functions in PG4. Signal Name PG4/T0/ SEG(32/23) PUOE LCDEN PUOV 0 DDOE LCDEN DDOV 1 PVOE 0 PVOV 0 PTOE – DIEOE LCDEN • (LCDPM) DIEOV 0 DI T0 INPUT AIO (1) AIO (2) 1.
Table 14-23. Overriding signals for alternate functions in PG3:0. Signal Name PG3/T1/ SEG(33/24) PG2/SEG(4/4) PG1/SEG(17/13) PG0/SEG(1814) PUOE LCDEN LCDEN LCDEN LCDEN PUOV 0 0 0 0 DDOE LCDEN LCDEN LCDEN LCDEN DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE LCDEN • (LCDPM) LCDEN LCDEN • (LCDPM) LCDEN • (LCDPM) DIEOV 0 0 0 0 DI T1 INPUT – – – SEG24 SEG4 SEG13 SEG14 LCDSEG LCDSEG LCDSEG LCDSEG AIO (1) AIO 14.3.8 (2) 1.
• PCINT21/SEG – Port H, Bit 5 PCINT21, Pin Change Interrupt Source 21: The PH5 pin can serve as an external interrupt source. SEG, LCD front plane 38. • PCINT20/SEG – Port H, Bit 4 PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as an external interrupt source. SEG, LCD front plane 39. • PCINT19/SEG – Port H, Bit 3 PCINT19, Pin Change Interrupt Source 19: The PH3 pin can serve as an external interrupt source. SEG, LCD front plane 7.
Table 14-26. Overriding signals for alternate functions in PH3:0 (Atmel ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P).
• PCINT27/SEG – Port J, Bit 3 PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source. SEG, LCD front plane 30. • PCINT26/SEG – Port J, Bit 2 PCINT26, Pin Change Interrupt Source 26: The PE26 pin can serve as an external interrupt source. SEG, LCD front plane 31. • PCINT25/SEG – Port J, Bit 1 PCINT25, Pin Change Interrupt Source 25: The PE25 pin can serve as an external interrupt source. SEG, LCD front plane 34.
Table 14-29. Overriding signals for alternate functions in PH3:0 (Atmel ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P).
14.4 14.4.1 Register description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
14.4.8 PORTC – Port C Data Register Bit 14.4.9 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 14.4.
14.4.16 PINE – Port E Input Pins Address Bit 7 6 5 4 3 2 1 0 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 0x0C (0x2C) 14.4.17 PORTF – Port F Data Register Bit 14.4.
14.4.24 DDRH – Port H Data Direction Register (1) Bit 7 6 5 4 3 2 1 0 DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xD9) 14.4.25 PINH – Port H Input Pins Address (1) Bit 7 6 5 4 3 2 1 0 PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A (0xD8) 14.4.26 14.4.27 14.4.
15. 8-bit Timer/Counter0 with PWM 15.1 Features • • • • • • • 15.2 Single Compare Unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) Overview Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 15-1.
event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. 15.2.2 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare unit number, in this case unit A. However, when using the register or bit defines in a program, the precise form must be used, i.e.
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk T0 ). clk T0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
15.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed.
15.5.2 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 15.5.
set as output before the OC0A value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. See See ”Register Description” on page 153.. 15.6.
Figure 15-5. CTC mode, timing diagram. OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
Figure 15-6. Fast PWM mode, timing diagram. OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 15-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation.
• OCR0A changes its value from MAX, like in Figure 15-7. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 15.
Figure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 15-11. Timer/Counter timing diagram, Clear Timer on Compare Match mode, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 15.9 15.9.
• Bit 5:4 – COM0A1:0: Compare Match Output Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting.
Table 15-6. Clock Select bit description. CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. 15.9.
16. 16-bit Timer/Counter1 16.1 Features • • • • • • • • • • • 16.
Figure 16-1. 16-bit Timer/Counter block diagram (1). Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 16.2.1 TCCRnB 1.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (”Analog Comparator” on page 203) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Figure 16-2. Counter Unit block diagram. DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock.
The Input Capture unit is illustrated by the block diagram shown in Figure 16-3. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 16-3. Input Capture Unit block diagram.
noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. 16.6.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme.
Figure 16-4. Output Compare Unit, block diagram. DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
16.7.3 Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare units, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values.
form Generation mode, but there are some exceptions. Refer to Table 16-2 on page 129, Table 16-3 and Table 164 for details. The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See ”Register description” on page 128 The COM1x1:0 bits have no effect on the Input Capture unit. 16.8.
Figure 16-6. CTC Mode, timing diagram. OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 16-8. Phase correct PWM mode, timing diagram. OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM.
The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Figure 16-9. Phase and frequency correct PWM mode, timing diagram. OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM).
opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 16.10 Timer/Counter timing diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering).
Figure 16-12. Timer/Counter timing diagram, no prescaling. clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx New OCRnx Value Old OCRnx Value (Update at TOP) Figure 16-13 shows the same timing data, but with the prescaler enabled. Figure 16-13. Timer/Counter timing diagram, with prescaler (fclk_I/O/8).
port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 16-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 16-2. Compare Output mode, non-PWM.
• Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 16-5 on page 130. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See ”Modes of Operation” on page 120.).
• Bit 6 – ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1).
Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 16.11.
16.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
17. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f CLK_I/O ).
clock frequency and duty cycle caused by Oscillator source (XTAL, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1 (1). clk I/O Clear PSR10 T0 Synchronization T1 Synchronization clkT1 Note: clkT0 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 17-1 on page 135.
17.4 17.4.1 Register description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode.
Table 17-2. Compare Output mode, non-PWM mode. COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC0A on compare match 1 0 Clear OC0A on compare match 1 1 Set OC0A on compare match Table 17-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 17-3. Compare Output mode, fast PWM mode (1). COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected.
• Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 17-5. Clock Select bit description. CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. 17.4.
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • • • • • • • 18.2 Single Compare Unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, phase correct Pulse Width Modulator (PWM) Frequency generator 10-bit clock prescaler Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A) Allows clocking from external 32kHz watch XTAL independent of the I/O Clock Overview Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module.
(ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter value at all times.
clkT2 Timer/Counter clock. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS2[2:0]). When no clock source is selected (CS2[2:0] = 0) the timer is stopped.
ering synchronizes the update of the OCR2A Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2A Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is disabled the CPU will access the OCR2A directly. 18.5.
Figure 18-4. Compare Match Output Unit, schematic. COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A[1:0] bits are set. However, the OC2A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
18.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM2[1:0] = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero.
18.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM2[1:0] = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A, and set at BOTTOM.
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A[1:0] bits.
data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register at the compare match between OCR2A and TCNT2 when the counter increments, and setting (or clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter decrements.
Figure 18-9. Timer/Counter timing diagram, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 18-10 shows the setting of OCF2A in all modes except CTC mode. Figure 18-10. Timer/Counter timing diagram, setting of OCF2A, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 18-11 on page 150 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 18-11.
18.9 Asynchronous operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2A, and TCCR2A. 4.
synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1.
18.10 Register Description 18.10.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
Table 18-3. Compare Output mode, non-PWM mode. (Continued) COM2A1 COM2A0 Description 0 1 Toggle OC2A on compare match. 1 0 Clear OC2A on compare match. 1 1 Set OC2A on compare match. Table 18-4 shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast PWM mode. Table 18-4. Compare Output mode, fast PWM mode (1).
18.10.2 TCNT2 – Timer/Counter Register Bit 7 6 5 4 (0xB2) 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare match on the following timer clock.
• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value.
18.10.7 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSR2 PSR10 Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware.
19. SPI – Serial Peripheral Interface 19.1 Features • • • • • • • • Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P and peripheral devices or between several AVR devices. A simplified block diagram of the Serial Peripheral Interface is shown in Figure 19-1 on page 158. The PRSPI bit in ”PRR – Power Reduction Register” on page 45 must be written to zero to enable the SPI module.
when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line.
Table 19-1. Pin SPI pin overrides (1). (Continued) Direction, Master SPI Direction, Slave SPI MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See ”Alternate functions of Port B” on page 74 for a detailed description of how to define the direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
19.3 19.3.1 SS pin functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
Figure 19-3. SPI transfer format with CPHA = 0. SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4. SPI transfer format with CPHA = 1.
19.5 19.5.1 Register description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 19-5. 19.5.2 Relationship between SCK and the oscillator frequency.
19.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
20. USART0 20.1 Features • • • • • • • • • • • • 20.
Figure 20-1. USART block diagram (1). Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1. Refer to Figure 1-2 on page 3 and ”Alternate functions of Port E” on page 80 for USART pin placement.
20.2.1 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver Operation However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
Signal description: 20.3.1 txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation.
20.3.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 20-2 on page 170 for details. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver.
munication line can be set to an idle (high) state. Figure 20-4 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 20-4. Frame formats. FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high.
The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
20.6 Data transmission – the USART transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
20.6.2 Sending frames with 9 data bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used.
The following code example shows a simple USART receive function that handles both nine bit characters and the status bits.
20.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
20.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 20.7.
Figure 20-5. Start bit sampling. RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 20-7. For Double Speed mode the first low level must be delayed to (B).
Table 20-3. Recommended maximum receiver baud rate error for Double Speed mode (U2Xn = 1). D # (Data+Parity Bit) Rslow (%) Rfast (%) Max. total error (%) Recommended max. receiver error (%) 5 94.12 105.66 +5.66/-5.88 ±2.5 6 94.92 104.92 +4.92/-5.08 ±2.0 7 95.52 104,35 +4.35/-4.48 ±1.5 8 96.00 103.90 +3.90/-4.00 ±1.5 9 96.39 103.53 +3.53/-3.61 ±1.5 10 96.70 103.23 +3.23/-3.30 ±1.
4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2.
Table 20-5. Examples of UBRRn settings for commonly used oscillator frequencies. (Continued) fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.
Table 20-6. Examples of UBRRn settings for commonly used oscillator frequencies. (Continued) fosc = 11.0592MHz fosc = 8.0000MHz Baud Rate (bps) U2Xn = 0 U2Xn = 1 U2Xn = 0 fosc = 14.7456MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.
Table 20-7. Examples of UBRRn settings for commonly used oscillator frequencies. (Continued) fosc = 16.0000MHz Baud Rate (bps) U2Xn = 0 fosc = 18.4320MHz U2Xn = 1 U2Xn = 0 fosc = 20.0000MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.
this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. 20.11.2 UCSRnA – USART Control and Status Register n A Bit 7 6 5 4 3 2 1 0 RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn Read/Write R R/W R R R R R/W R/W Initial Value 0 0 1 0 0 0 0 0 UCSRnA • Bit 7 – RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e.
unaffected by the MPCMn setting. For more detailed information see ”Multi-processor Communication Mode” on page 184. 20.11.3 UCSRnB – USART Control and Status Register n B Bit 7 6 5 4 3 2 1 0 RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 UCSRnB • Bit 7 – RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag.
20.11.4 UCSRnC – USART Control and Status Register n C Bit 7 6 5 4 3 2 1 0 – UMSELn UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC • Bit 6 – UMSELn: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Figure 20-8. UMSELn bit settings.
Figure 20-11. UCSZ bits settings. (Continued) UCSZn2 UCSZn1 UCSZn0 Character size 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Figure 20-12. UCPOLn bit settings.
21. USI – Universal Serial Interface Features • • • • • • Overview The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load.
number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. 21.3 21.3.
The Three-wire mode timing is shown in Figure 21-3 on page 194 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e.
ldi r16,(1<
21.3.4 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 21-4. Two-wire mode operation, simplified diagram.
Referring to the timing diagram (Figure 21-5 on page 197), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the Data Direction Register bit must be set to one for the output to be enabled.
21.4 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 21.4.1 Half-duplex Asynchronous Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 21.4.2 4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
21.5.2 USISR – USI Status Register Bit 7 6 5 4 3 2 1 0 USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB9) USISR The Status Register contains Interrupt Flags, line Status Flags and the counter value. • Bit 7 – USISIF: Start Condition Interrupt Flag When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is detected.
• Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt. If there is a pending interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. Refer to the USISIF bit description on page 200 for further details. • Bit 6 – USIOIE: Counter Overflow Interrupt Enable Setting this bit to one enables the Counter Overflow interrupt.
• Bit 3:2 – USICS[1:0]: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1:0 bits enables software strobe option.
22. Analog Comparator 22.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Table 22-1. 22.3 22.3.1 Analog Comparator multiplexed input.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator.
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 23. Analog to Digital Converter 23.1 Features • • • • • • • • • • • • • 23.2 10-bit resolution 0.
Figure 23-1. Analog to Digital Converter, block schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADIF ADPS2 ADATE ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. 23.
Prescaling and Conversion Timing Figure 23-3. ADC prescaler. ADEN START Reset 7-BIT ADC PRESCALER CK/128 CK/64 CK/32 CK/16 CK/8 CK/4 CK CK/2 23.5 ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
Figure 23-4. ADC timing diagram, first conversion (Single Conversion mode). Next Conversion First Conversion Cycle Number 1 2 12 13 14 16 15 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample & Hold MUX and REFS Update Figure 23-5. ADC timing diagram, single conversion.
Figure 23-7. ADC timing diagram, free running conversion. One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 23-1. ADC conversion time. Condition Sample and Hold (cycles from start of conversion) Conversion time (cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 Auto Triggered conversions 23.
In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC.
mended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 23-8. Analog input circuitry. IIH ADCn 1..
Figure 23-9. ADC power connections. GND 52 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 10μΗ GND AVCC 100nF Analog Ground Plane 23.7.3 51 63 64 1 LCDCAP PA0 VCC ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 23-11. Gain error. Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB Figure 23-12.
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB Figure 23-13. Differential non-linearity (DNL). Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.
Figure 23-14. Differential measurement range. Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts) 0x200 Table 23-2. Correlation between input voltage and output codes. VADCn Read code VADCm + VREF VADCm + 511 VADCm + 510 Corresponding decimal value 0x1FF 511 /512 VREF 0x1FF 511 /512 VREF 0x1FE 510 ... ... ... VADCm + 1/512 VREF 0x001 1 VADCm 0x000 0 VADCm - /512 VREF 0x3FF -1 ... ... ...
23.9 23.9.1 Register description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 23-3 on page 218.
Table 23-4. Input channel selections.
23.9.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
23.9.3 ADCL and ADCH – The ADC Data Register 23.9.3.1 ADLAR = 0 Bit 15 14 13 12 11 10 9 8 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 23.9.3.
Table 23-7. 23.9.5 ADC auto trigger source selections.
24. LCD Controller 24.1 Features • • • • • • • • • • • • 24.
Figure 24-1. LCD Module, block diagram.
Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0 compared to none addressed COM lines. Non-energized segments are in phase with the addressed COM0, and energized segments have opposite phase and large amplitude. For waveform figures refer to ”Mode of operation” on page 226. Latched data from LCDDR4 - LCDDR0 is multiplexed into the decoder. The decoder is controlled from the LCD timing and sets up signals controlling the analog switches to produce an output waveform.
24.3 24.3.1 Mode of operation Static Duty and Bias If all segments on a LCD have one electrode common, then each segment must have a unique terminal. This kind of display is driven with the waveform shown in Figure 24-3. SEG0 - COM0 is the voltage across a segment that is on, and SEG1 - COM0 is the voltage across a segment that is off. Figure 24-3. Driving a LCD with one common terminal.
Figure 24-5. Driving a LCD with three common terminals. VLCD 2/ V 3 LCD 1/ V 3 LCD SEG0 GND GND VLCD 2/ V 3 LCD 1/ V 3 LCD VLCD 2/ V 3 LCD 1/ V 3 LCD COM0 GND GND VLCD 2/ V 3 LCD 1/ V 3 LCD VLCD 2/ V 3 LCD 1/ V 3 LCD SEG0 - COM0 GND -1/3VLCD -2/3VLCD -VLCD 24.3.4 VLCD 2/ V 3 LCD 1/ V 3 LCD Frame Frame GND -1/3VLCD -2/3VLCD -VLCD SEG0 COM1 SEG0 - COM1 Frame Frame 1/4 Duty and 1/3 Bias 1/3 bias is optimal for LCD displays with four common terminals (1/4 duty).
Figure 24-7. Default and low power waveform. VLCD 2/ V 3 LCD 1/ V 3 LCD GND GND VLCD 2/ V 3 LCD 1/ V 3 LCD VLCD 2/ V 3 LCD 1/ V 3 LCD COM0 GND GND VLCD 2/ V 3 LCD 1/ V 3 LCD VLCD 2/ V 3 LCD 1/ V 3 LCD GND -1/3VLCD -2/3VLCD -VLCD 24.3.
Figure 24-8. LCD. LCD 2a 1b 2f 2b 2g 1c 2e 2c 51 COM2 COM1 COM0 2d 50 49 COM3 48 SEG0 47 ATmega329 SEG2 2f 2g .. SEG1 2c 2d 2e SEG0 SEG1 46 1b,1c 2a 2b COM0 COM1 COM2 Connection table SEG2 45 Display: TN Positive, Reflective Number of common terminals: 3 Number of segment terminals: 21 Bias system: 1/3 Bias Drive system: 1/3 Duty Operating voltage: 3.0 ±0.
Assembly code example (1) LCD_Init: ; Use 32 kHz crystal oscillator ; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins ldi r16, (1<
ress. To avoid this, an interrupt routine can be used to update Display memory, LCD Blanking, Low power waveform, and contrast control, just after data are latched. In the example below we assume SEG10 and COM1 and SEG4 in COM0 are the only segments changed from frame to frame. Data are stored in r20 and r21 for simplicity Assembly code example (1) LCD_update: ; LCD Blanking and Low power waveform are unchanged. ; Update Display memory.
Assembly code example (1) LCD_disable: ; Wait until a new frame is started. Wait_1: lds r16, LCDCRA sbrs r16, LCDIF rjmp Wait_1 ; Set LCD Blanking and clear interrupt flag ; by writing a logical one to the flag. ldi r16, (1<
24.5 24.5.1 Register description LCDCRA – LCD Control and Status Register A Bit 7 6 5 4 3 2 1 0 LCDEN LCDAB – LCDIF LCDIE LCDBD LCDCCD LCDBL Read/Write R/W R/W R R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 (0xE4) LCDCRA • Bit 7 – LCDEN: LCD Enable Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned off immediately.
24.5.2 LCDCRB – LCD Control and Status Register B Bit 7 6 5 4 3 2 1 0 LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xE5) Note: LCDCRB Bit 3, LCDPM3 is only available in Atmel ATmega3290A/3290PA/6490A/6490P. • Bit 7 – LCDCS: LCD Clock Select When this bit is written to zero, the system clock is used. When this bit is written to one, the external asynchronous clock source is used.
Table 24-3. LCDPM3 LCDPM2 LCDPM1 LCDPM0 I/O port in use as segment driver Maximum number of segments 1 0 0 1 SEG0:28 29 1 0 1 0 SEG0:30 31 1 0 1 1 SEG0:32 33 1 1 0 0 SEG0:34 35 1 1 0 1 SEG0:36 37 1 1 1 0 SEG0:38 39 1 1 1 1 SEG0:39 40 Note: 24.5.3 LCD Port Mask (Values in bold are only available in the Atmel ATmega3290A/3290PA/6490A/6490P) (Continued) 1. LCDPM3 is reserved and will always read as zero in Atmel ATmega329A/329PA/649A/649P.
Table 24-5. LCD clock divide LCDCD2 LCDCD1 LCDCD0 Output from Prescaler divided by (D): 0 0 0 1 256Hz 0 0 1 2 128Hz 0 1 0 3 85.3Hz 0 1 1 4 64Hz 1 0 0 5 51.2Hz 1 0 1 6 42.7Hz 1 1 0 7 36.6Hz 1 1 1 8 32Hz clkLCD = 32.768kHz, N = 16, and Duty = 1/4, gives a frame rate of: The frame frequency can be calculated by the following equation: f clk LCD f frame = ------------------------K N D Where: N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048 or 4096).
resistance may need longer drive time to achieve satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD clock period, even if the selected drive time is longer. When using static duty or blanking, drive time will always be one half prescaled LCD clock period. New values take effect immediately, and can cause small glitches in the display output. This can be avoided by setting the LCDBL in LCDCRA, and wait to the next start of frame before changing LCDDC[2:0].
Table 24-8. 24.5.5 LCD contrast control. (Continued) LCDCC3 LCDCC2 LCDCC1 LCDCC0 Maximum voltage VLCD 1 1 0 1 3.25 1 1 1 0 3.30 1 1 1 1 3.35 LCD Memory Mapping Write a LCD memory bit to one and the corresponding segment will be energized (visible). Unused LCD Memory bits for the actual display can be used freely as storage.
25. JTAG Interface and On-chip Debug System 25.1 Features • JTAG (IEEE std. 1149.1 Compliant) interface • Boundary-scan capabilities according to the IEEE std. 1149.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCR is cleared, the TAP pins are internally pulled high and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this fuse programmed. For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debugger to be able to detect external reset sources.
Figure 25-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 25.4 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system.
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – ShiftDR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high.
level execution of Assembly programs assembled with Atmel Corporation’s AVR Assembler and C programs compiled with third party vendors’ compilers. The Atmel AVR Studio runs under Microsoft® Windows® 95/98/2000, Windows NT® and Windows XP®. For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only highlights are presented in this document. All necessary execution commands are available in AVR Studio, both on source level and on disassembly level.
• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993 Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992. 25.10 Register description 25.10.
26. IEEE 1149.1 (JTAG) Boundary-scan 26.1 Features • • • • • 26.2 JTAG (IEEE std. 1149.
26.3 Data registers The data registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain 26.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested.
Figure 26-1. Reset register. To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 26.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See ”Boundary-scan Chain” on page 248 for a complete description. 26.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input 26.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
Figure 26-2. Boundary-scan cell for bi-directional Port Pin with Pull-up function.
Figure 26-3. General Port Pin, schematic diagram. See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR WDx RESET OCxn DATA BUS RDx Pxn 1 Q ODxn IDxn D 0 PORTxn Q CLR RESET SLEEP WPx RRx SYNCHRONIZER D Q L Q D WRx RPx Q PINxn Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 26.5.
Figure 26-5 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell. In addition to the main clock, the timer Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this Oscillator does not have external connections. Figure 26-5. Boundary-scan cells for oscillators and clock options.
Figure 26-6. Analog Comparator. BANDGAP REFERENCE ACBG ACD ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 26-7. General Boundary-scan cell used for signals for Comparator and ADC.
Table 26-3. 26.5.5 Boundary-scan signals for the Analog Comparator.
Table 26-4. Boundary-scan signals for the ADC (1).
Table 26-4. Boundary-scan signals for the ADC (1).
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC. The lower limit is: The upper limit is: 1024 1.5V 0.95 5V = 291 = 0x123 1024 1.5V 1.05 5V = 323 = 0x143 The recommended values from Table 26-4 on page 254 are used unless other values are given in the algorithm in Table 26-5. Only the DAC and port pin values of the Scan Chain are shown.
26.6 Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P Boundary-scan order Table 26-7 on page 263 and Table 26-8 on page 270 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
Table 26-6. Atmel ATmega169A/169PA Boundary-scan order.
Table 26-6. Atmel ATmega169A/169PA Boundary-scan order. (Continued) Bit number Signal name 157 PE0.Data 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pull-up_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pull-up_Enable 139 PE6.Data 138 PE6.Control 137 PE6.Pull-up_Enable 136 PE7.
Table 26-6. Atmel ATmega169A/169PA Boundary-scan order. (Continued) Bit number Signal name Module 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pull-up_Enable 115 PB6.Data 114 PB6.Control 113 PB6.Pull-up_Enable 112 PB7.
Table 26-6. Atmel ATmega169A/169PA Boundary-scan order. (Continued) Bit number Signal name 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pull-up_Enable 77 PD5.Data 76 PD5.Control 75 PD5.Pull-up_Enable 74 PD6.Data 73 PD6.
Table 26-6. Atmel ATmega169A/169PA Boundary-scan order. (Continued) Bit number Signal name 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pull-up_Enable 44 PC6.Data 43 PC6.Control 42 PC6.Pull-up_Enable 41 PC7.Data 40 PC7.Control 39 PC7.Pull-up_Enable 38 PG2.
Table 26-6. Atmel ATmega169A/169PA Boundary-scan order. (Continued) Bit number Signal name 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.Pull-up_Enable 5 PF1.Data 4 PF1.Control 3 PF1.Pull-up_Enable 2 PF0.
Table 26-7. Atmel ATmega329A/329PA/649A/649P Boundary-scan order, 64-pin.
Table 26-7. Atmel ATmega329A/329PA/649A/649P Boundary-scan order, 64-pin. (Continued) Bit number Signal name 157 PE0.Data 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pull-up_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pull-up_Enable 139 PE6.Data 138 PE6.Control 137 PE6.
Table 26-7. Atmel ATmega329A/329PA/649A/649P Boundary-scan order, 64-pin. (Continued) Bit number Signal name Module 133 PB0.Data 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pull-up_Enable 115 PB6.Data 114 PB6.Control 113 PB6.
Table 26-7. Atmel ATmega329A/329PA/649A/649P Boundary-scan order, 64-pin. (Continued) Bit number Signal name 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pull-up_Enable 77 PD5.Data 76 PD5.Control 75 PD5.Pull-up_Enable 74 PD6.
Table 26-7. Atmel ATmega329A/329PA/649A/649P Boundary-scan order, 64-pin. (Continued) Bit number Signal name 62 PC0.Data 61 PC0.Control 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pull-up_Enable 44 PC6.Data 43 PC6.Control 42 PC6.Pull-up_Enable 41 PC7.
Table 26-7. Atmel ATmega329A/329PA/649A/649P Boundary-scan order, 64-pin. (Continued) Bit number Signal name 28 PA5.Control 27 PA5.Pull-up_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.
Table 26-8. Atmel ATmega3290A/3290PA/6490A/6490P Boundary-scan order, 100-pin.
Table 26-8. Atmel ATmega3290A/3290PA/6490A/6490P Boundary-scan order, 100-pin. (Continued) Bit number Signal name 207 NEGSEL_0 206 PASSEN 205 PRECH 204 ST 203 VCCREN 202 PE0.Data 201 PE0.Control 200 PE0.Pull-up_Enable 199 PE1.Data 198 PE1.Control 197 PE1.Pull-up_Enable 196 PE2.Data 195 PE2.Control 194 PE2.Pull-up_Enable 193 PE3.Data 192 PE3.Control 191 PE3.Pull-up_Enable 190 PE4.Data 189 PE4.Control 188 PE4.Pull-up_Enable 187 PE5.Data 186 PE5.Control 185 PE5.
Table 26-8. Atmel ATmega3290A/3290PA/6490A/6490P Boundary-scan order, 100-pin. (Continued) Bit number Signal name Module 171 PB0.Control 170 PB0.Pull-up_Enable 169 PB1.Data 168 PB1.Control 167 PB1.Pull-up_Enable 166 PB2.Data 165 PB2.Control 164 PB2.Pull-up_Enable 163 PB3.Data 162 PB3.Control 161 PB3.Pull-up_Enable 160 PB4.Data 159 PB4.Control 158 PB4.Pull-up_Enable 157 PB5.Data 156 PB5.Control 155 PB5.Pull-up_Enable 154 PB6.Data 153 PB6.Control 152 PB6.
Table 26-8. Atmel ATmega3290A/3290PA/6490A/6490P Boundary-scan order, 100-pin. (Continued) Bit number Signal name 135 EXTCLK (XTAL1) 134 OSCCK 133 RCCK 132 OSC32CK 131 PJ2.Data 130 PJ2.Control 129 PJ2.Pull-up_Enable 128 PJ3.Data 127 PJ3.Control 126 PJ3.Pull-up_Enable 125 PJ4.Data 124 PJ4.Control 123 PJ4.Pull-up_Enable 122 PJ5.Data 121 PJ5.Control 120 PJ5.Pull-up_Enable 119 PJ6.Data 118 PJ6.Control 117 PJ6.Pull-up_Enable 116 PD0.Data 115 PD0.Control 114 PD0.
Table 26-8. Atmel ATmega3290A/3290PA/6490A/6490P Boundary-scan order, 100-pin. (Continued) Bit number Signal name 99 PD5.Pull-up_Enable 98 PD6.Data 97 PD6.Control 96 PD6.Pull-up_Enable 95 PD7.Data 94 PD7.Control 93 PD7.Pull-up_Enable 92 PG0.Data 91 PG0.Control 90 PG0.Pull-up_Enable 89 PG1.Data 88 PG1.Control 87 PG1.Pull-up_Enable 86 PC0.Data 85 PC0.Control 84 PC0.Pull-up_Enable 83 PC1.Data 82 PC1.Control 81 PC1.Pull-up_Enable 80 PC2.Data 79 PC2.Control 78 PC2.
Table 26-8. Atmel ATmega3290A/3290PA/6490A/6490P Boundary-scan order, 100-pin. (Continued) Bit number Signal name 63 PH1.Pull-up_Enable 62 PH2.Data 61 PH2.Control 60 PH2.Pull-up_Enable 59 PH3.Data 58 PH3.Control 57 PH3.Pull-up_Enable 56 PC6.Data 55 PC6.Control 54 PC6.Pull-up_Enable 53 PC7.Data 52 PC7.Control 51 PC7.Pull-up_Enable 50 PG2.Data 49 PG2.Control 48 PG2.Pull-up_Enable 47 PA7.Data 46 PA7.Control 45 PA7.Pull-up_Enable 44 PA6.Data 43 PA6.Control 42 PA6.
Table 26-8. Atmel ATmega3290A/3290PA/6490A/6490P Boundary-scan order, 100-pin. (Continued) Bit number Signal name 27 PA1.Pull-up_Enable 26 PA0.Data 25 PA0.Control 24 PA0.Pull-up_Enable 23 PH4.Data 22 PH4.Control 21 PH4.Pull-up_Enable 20 PH5.Data 19 PH5.Control 18 PH5.Pull-up_Enable 17 PH6.Data 16 PH6.Control 15 PH6.Pull-up_Enable 14 PH7.Data 13 PH7.Control 12 PH7.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.
26.8 26.8.1 Register description MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled.
27. Boot Loader Support – Read-While-Write Self-Programming 27.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot memory size High security (separate Boot Lock Bits for a flexible protection) Separate fuse to select reset vector Optimized page (1) size Code efficient algorithm Efficient Read-Modify-Write Support Note: 27.2 1. A page is a section in the Flash consisting of several bytes (see Table 28-13 on page 306) used during programming.
• When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation • When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation.
Figure 27-1. Read-While-Write vs. no Read-While-Write.
Figure 27-2. Memory sections.
Table 27-2. Boot Lock Bit0 Protection Modes (Application Section) (1). BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
27.6 Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code.
Figure 27-3. Addressing the Flash during SPM (1). BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PCWORD WORD ADDRESS WITHIN A PAGE PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: 27.8 1. The different variables used in Figure 27-3 on page 284 are listed in Table 27-11 on page 291. 2. PCPAGE and PCWORD are listed in Table 28-13 on page 306.
27.8.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase • Page Erase to the NRWW section: The CPU is halted during the operation 27.
27.8.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. Bit 7 6 5 4 3 2 1 0 R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1 See Table 27-2 and Table 27-3 on page 282 for how the different settings of the Boot Loader bits affect the Flash access. If bits 5...
(EFB) will be loaded in the destination register as shown below. Refer to Table 28-3 on page 294 for detailed description and mapping of the Extended Fuse byte. Bit 7 6 5 4 3 2 1 0 Rd – – – – – EFB2 EFB1 EFB0 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. 27.8.
.org SMALLBOOTSTART Write_page: ; Page Erase ldi spmcrval, (1<
sbrc temp1, SPMEN rjmp Wait_spm ; input: spmcrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence out SPMCSR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret 27.8.13 Boot Loader Parameters 27.8.13.
Table 27-8. Explanation of different variables used in Figure 27-3 on page 284 and the mapping to the Z-pointer (Atmel ATmega169A/169PA) (1). Corresponding Z-value Variable Description PCMSB 12 Most significant bit in the Program Counter. (The Program Counter is 13 bits PC[12:0]) PAGEMSB 5 Most significant bit which is used to address the words within one page (64 words in a page requires six bits PC [5:0]). ZPCMSB Z13 Bit in Z-register that is mapped to PCMSB.
Table 27-11. Explanation of different variables used in Figure 27-3 on page 284 and the mapping to the Z-pointer (Atmel ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P) (1). Corresponding Z-value Variable Description PCMSB 13 Most significant bit in the Program Counter. (Program Counter is 14 bits PC[13:0]) PAGEMSB 5 Most significant bit which is used to address the words within one page (64 words in a page requires six/seven bits PC [5:0]).
SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost.
28. Memory programming 28.1 Program and Data Memory Lock Bits The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 28-1. Lock Bit byte (1).
Lock Bit Protection modes (1)(2). (Continued) Table 28-2. Memory Lock bits 2 Notes: 28.2 Protection type 1 0 SPM is not allowed to write to the Boot Loader section. 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
Table 28-4. Fuse High byte. Fuse High byte Bit no. Description Default value OCDEN (4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN (5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN (1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
28.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 28.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
28.6 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P. Pulses are assumed to be at least 250ns unless otherwise noted. 28.6.
Table 28-9. Pin name mapping. (Continued) Signal name in programming mode Pin name I/O PAGEL PD7 I Program Memory and EEPROM data Page Load. BS2 PA0 I Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte). DATA PB7-0 I/O Function Bi-directional Data bus (Output when OE is low). Table 28-10. Pin values used to enter programming mode. Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 28-11.
1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 28-10 on page 298 to “0000” and wait at least 100ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5. Wait at least 50µs before sending a new command. 28.7.
C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch Data 1. Set BS1 to “1”. This selects high data byte. 2. Give PAGEL a positive pulse.
Figure 28-2. Addressing the Flash which is organized in pages (1). PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 28-7 on page 296. Figure 28-3. Programming the Flash waveforms (1). F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR.
28.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 28-8 on page 296. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to ”Programming the Flash” on page 299 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
28.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash” on page 299 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 28.7.
Figure 28-5. Programming the FUSES waveforms. Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 28.7.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on page 299 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte.
Figure 28-6. Mapping between BS1, BS2 and the Fuse and Lock bits during read. 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte BS1 1 BS2 28.7.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on page 299 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”.
Figure 28-8. Parallel programming timing, loading sequence with timing requirements (1). LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 28-7 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 28-9.
Table 28-13. Parallel programming characteristics, VCC = 5V ±10%. (Continued) Symbol Parameter tBVPH BS1 Valid before PAGEL High 67 tPHPL PAGEL Pulse Width High 150 tPLBX BS1 Hold after PAGEL Low 67 tWLBX BS2/1 Hold after WR Low 67 tPLWL PAGEL Low to WR Low 67 tBVWL BS1 Valid to WR Low 67 tWLWH WR Pulse Width Low 150 tWLRL WR Low to RDY/BSY Low (1) WR Low to RDY/BSY High tWLRH (2) Typ. Max. Units ns 0 1 3.7 4.5 7.
Figure 28-10. Serial programming and verify (1). +1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI AVCC MISO SCK XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V.
the Write Program Memory Page instruction with the 8MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 28-15.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction.
Table 28-16. Serial programming instruction set.
Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 28-12 on page 311. Figure 28-12. Serial programming instruction, example.
28.9 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
Figure 28-13. State machine sequence for changing the instruction word. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 28.9.2 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
• Capture-DR: The result of the previous command is loaded into the Data Register • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command • Update-DR: The programming command is applied to the Flash inputs • Run-Test/Idle: One clock cycle is generated, executing the applied command (not always required, see Table 2817 on page 317) 28.9.
28.9.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section ”Programming Specific JTAG Instructions” on page 312. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 28.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode.
Figure 28-15. Programming Command register.
Table 28-17. JTAG programming instruction set. a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b.
Table 28-17. JTAG programming instruction set. (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c.
Table 28-17. JTAG programming instruction set. (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence Notes xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b.
Figure 28-16. State machine sequence for changing/reading the data word. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 28.9.
Figure 28-17. Flash Data byte register. STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automatically feeds the state machine for the Flash Data Byte Register with sufficient number of clock pulses to complete its operation transparently for the user.
1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address High byte using programming instruction 2b. 4. Load address Low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to Table 28-13 on page 306).
28.9.18 Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip Erase” on page 321. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address High byte using programming instruction 4b. 4. Load address Low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7.
28.9.22 Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8e. To only read Fuse High byte, use programming instruction 8b. To only read Fuse Low byte, use programming instruction 8c. To only read Lock bits, use programming instruction 8d. 28.9.23 Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2.
29. Electrical characteristics – TA = -40°C to 85°C 29.1 Absolute maximum ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Table 29-1. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). (Continued) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Typ. Max. Units <10 40 mV 50 nA -50 750 500 ns 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min.
29.2.2 ATmega169PA DC Characteristics Table 29-3. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Condition Power Supply Current (1) ICC Power-save mode (2) Power-down mode (2) Notes: Typ. Max. Active 1MHz, VCC = 2V 0.35 0.44 Active 4MHz, VCC = 3V 2.3 2.5 Active 8MHz, VCC = 5V 8.4 9.5 Idle 1MHz, VCC = 2V 0.1 0.2 Idle 4MHz, VCC = 3V 0.7 0.8 Idle 8MHz, VCC = 5V 3.0 3.3 32kHz TOSC enabled, VCC = 1.8V 0.55 32kHz TOSC enabled, VCC = 3V 0.
29.2.4 ATmega329PA DC Characteristics Table 29-5. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Power Supply Current (1) ICC Power-save mode Power-down mode (1) Notes: Condition Min. Typ. Max. Active 1MHz, VCC = 2V 0.37 0.55 Active 4MHz, VCC = 3V 2.4 2.9 Active 8MHz, VCC = 5V 5.3 11.0 Idle 1MHz, VCC = 2V 0.14 0.25 Idle 4MHz, VCC = 3V 0.6 0.9 Idle 8MHz, VCC = 5V 1.6 3.5 32kHz TOSC enabled, VCC = 1.8V 0.75 32 kHz TOSC enabled, VCC = 3V 0.
29.2.5 ATmega3290A DC Characteristics Table 29-6. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Power Supply Current ICC Power-save mode Power-down mode Notes: Min. Typ. Max. Active 1MHz, VCC = 2V 0.8 1.5 Active 4MHz, VCC = 3V 2.6 3.5 Active 8MHz, VCC = 5V 6.0 12.0 Idle 1MHz, VCC = 2V 0.2 0.45 Idle 4MHz, VCC = 3V 0.7 1.5 Idle 8MHz, VCC = 5V 1.8 5.5 32kHz TOSC enabled, VCC = 1.8V 0.75 32kHz TOSC enabled, VCC = 3V 0.
29.2.7 ATmega649A DC Characteristics Table 29-8. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Power Supply Current ICC Power-save mode Power-down mode Notes: Min. Typ. Max. Active 1MHz, VCC = 2V 1.1 1.5 Active 4MHz, VCC = 3V 2.8 3.5 Active 8MHz, VCC = 5V 7.0 12.0 Idle 1MHz, VCC = 2V 0.3 0.45 Idle 4MHz, VCC = 3V 0.8 1.5 Idle 8MHz, VCC = 5V 2.5 5.5 32kHz TOSC enabled, VCC = 1.8V 0.75 32kHz TOSC enabled, VCC = 3V 0.
29.2.9 ATmega6490A DC Characteristics Table 29-10. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Symbol Parameter Power Supply Current ICC Power-save mode Power-down mode Notes: Condition Min. Typ. Max. Active 1MHz, VCC = 2V 1.1 1.5 Active 4MHz, VCC = 3V 2.8 3.5 Active 8MHz, VCC = 5V 7.0 12.0 Idle 1MHz, VCC = 2V 0.3 0.45 Idle 4MHz, VCC = 3V 0.8 1.5 Idle 8MHz, VCC = 5V 2.5 5.5 32kHz TOSC enabled, VCC = 1.8V 0.75 32kHz TOSC enabled, VCC = 3V 0.
29.3 Speed Grades Maximum frequency is depending on VCC. As shown in Figure 29-1, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7 and between 2.7V < VCC < 4.5. Figure 29-1. Maximum frequency vs. VCC, Atmel ATmega169A/169PA/ATmega649A/ATmega649P. 16MHz 8MHz Safe operating area 4MHz 1.8V 2.7V 4.5V 5.5V Figure 29-2. Maximum frequency vs. VCC (0 - 20MHz) Atmel ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA/ATmega6490A/ ATmega6490P. 20MHz 10MHz Safe operating area 4MHz 1.
29.4 29.4.1 Clock characteristics Calibrated internal RC oscillator accuracy Table 29-12. Calibration accuracy of internal RC oscillator. Frequency VCC Temperature Calibration accuracy 8.0MHz 3V 25C ±10% 7.3 - 8.1MHz 1.8V - 5.5V (1) -40C - 85C ±1% Factory calibration User calibration Notes: 29.4.2 1. Voltage range for Atmel ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P. External clock drive waveforms Figure 29-3. External clock drive waveforms. V IH1 V IL1 29.4.
29.5 System and reset characteristics Table 29-14. Reset, Brown-out, and Internal Voltage characteristics. Symbol VPOT Condition Min. Typ. Max. Power-on Reset Threshold Voltage (rising) TA = -40°C to 85°C 1.1 1.4 1.6 Power-on Reset Threshold Voltage (falling) (1) TA = -40°C to 85°C 0.6 1.3 1.6 VPSR Power-on Reset Slope Rate VRST RESET Pin Threshold Voltage VCC = 3V tRST Minimum pulse width on RESET Pin VCC = 3V VHYST Units V 0.1 4.5 V/ms 0.2 VCC 0.9 VCC V 2.
29.8 SPI Timing Characteristics See Figure 29-4 on page 335 and Figure 29-5 on page 336 for details. Table 29-17. SPI timing parameters. Description Mode 1 SCK period Master See Table 19-5 on page 166 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 29-5. SPI interface timing requirements (Slave mode). SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 17 15 MISO (Data Output) MSB ...
29.9 ADC characteristics Table 29-18. ADC characteristics. Symbol Parameter Condition Min. Typ. Single Ended Conversion 10 Differential Conversion 8 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 Max. Resolution Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) Units Bits Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz 2.5 2.
29.10 LCD controller characteristics Table 29-19. LCD controller characteristics Symbol Parameter Condition Total for All COM and SEG pins Min. Typ. ILCD LCD Driver Current RSEG Segment Driver Output Impedance 10 RCOM Blackplane Driver Output Impedance 2 Max.
30. Electrical Characteristics – TA = -40°C to 105°C 30.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
Table 30-1. TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Note: Min. Typ. Max. Units <10 40 mV 50 nA -50 750 500 ns 1. “Max” means the highest value where the pin is guaranteed to be read as low 2.
30.2.2 Current consumption ATmega329A Table 30-3. Symbol Current consumption ATmega329A TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-save mode Condition Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.35 0.55 mA Active 4MHz, VCC = 3V 1.65 2.9 mA Active 8MHz, VCC = 5V 5.7 11 mA Idle 1MHz, VCC = 2V 0.1 0.2 mA Idle 4MHz, VCC = 3V 0.4 0.90 mA Idle 8MHz, VCC = 5V 1.65 3.5 mA 32kHz TOSC enabled, VCC = 1.
30.2.4 Current consumption ATmega329PA Table 30-5. Symbol Current consumption ATmega329PA TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-save mode Condition Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.35 0.55 mA Active 4MHz, VCC = 3V 1.65 2.9 mA Active 8MHz, VCC = 5V 5.7 11 mA Idle 1MHz, VCC = 2V 0.1 0.2 mA Idle 4MHz, VCC = 3V 0.4 0.90 mA Idle 8 Hz, VCC = 5V 1.65 3.5 mA 32kHz TOSC enabled, VCC = 1.
30.2.6 Current consumption ATmega3290P Table 30-7. Symbol Current consumption ATmega3250P TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-save mode Power-down mode Note: Condition Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.4 0.85 mA Active 4MHz, VCC = 3V 2.3 3.8 mA Active 8MHz, VCC = 5V 9 14 mA Idle 1MHz, VCC = 2V 0.1 0.3 mA Idle 4MHz, VCC = 3V 0.8 1.65 mA Idle 8MHz, VCC = 5V 3.1 5.
31. Typical Characteristics – TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
Figure 31-2. Atmel ATmega169A: Active supply current vs. frequency (1 - 16MHz). 11 10 5.5V 9 5.0V 8 4.5V ICC [mA] 7 6 4.0V 5 4 3.3V 3 2.7V 2 1 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency [MHz] Figure 31-3. ATmega169A: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 6 85°C 25°C -45°C 5 ICC [mA] 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-4. Atmel ATmega169A: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 1.4 25°C 85°C -45°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-5. ATmega169A: Active supply current vs. VCC (32kHz watch XTAL). 40 85°C 25°C -45°C 35 30 ICC [µA] 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle supply current Figure 31-6. Atmel ATmega169A: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.25 5.5V ICC [mA] 0.20 5.0V 4.5V 0.15 4.0V 3.3V 0.10 2.7V 0.05 1.8V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-7. ATmega169A: Idle supply current vs. frequency (1 - 16MHz). 3.5 5.5V 3.0 5.0V 4.5V 2.5 ICC [mA] 31.1.2 2.0 4.0V 1.5 3.3V 1.0 2.7V 0.5 1.
Figure 31-8. Atmel ATmega169A: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.00 25°C 85°C 1.75 -45°C 1.50 ICC [mA] 1.25 1.00 0.75 0.50 0.25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-9. ATmega169A: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 0.40 85°C 25°C -45°C 0.35 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-10. Atmel ATmega169A: Idle supply current vs. VCC (32kHz watch XTAL). 9 85°C 25°C -45°C 8 7 ICC [µA] 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 31.1.3 ATmega169A: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
31.1.3.1 Example 1 Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI enabled at VCC = 3.0V and F = 1MHz. From Table 31-2, second column, we see that we need to add 13.1% for the USART0, 13.0% for the SPI, and 13.2% for the TIMER1 module. Reading from Figure 31-6, we find that the idle current consumption is ~0.09 mA at VCC = 3.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and SPI enabled, gives: I CC total 0.09mA 1 + 0.131 + 0.
31.1.5 Power-save supply current Figure 31-13. Atmel ATmega169A: Power-save supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 2.0 85°C 1.8 1.6 ICC [µA] 1.4 1.2 25°C 1.0 -45°C 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby supply current Figure 31-14. ATmega169A standby supply current vs.
Figure 31-15. Atmel ATmega169A: Standby supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.18 6MHz_res 6MHz_xtal 0.16 4MHz_xtal 4MHz_res 0.14 ICC [mA] 0.12 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.10 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Pin pull-up Figure 31-16. ATmega169A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 150 125 100 IOP [µA] 31.1.7 75 50 25°C 85°C -45°C 25 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-17. Atmel ATmega169A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 20 85°C 25°C -45°C 10 0 0 0.5 1 1.5 2 2.5 3 VOP [V] Figure 31-18. ATmega169A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 IOP [µA] 35 30 25 20 15 10 25°C 85°C -45°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 31-19. Atmel ATmega169A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 120 100 IRESET [µA] 80 60 40 25°C 85°C -45°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET [V] Figure 31-20. ATmega169A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C 85°C -45°C 10 0 0 0.5 1 1.5 2 2.
Figure 31-21. Atmel ATmega169A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 40 35 IRESET [µA] 30 25 20 15 10 25°C 85°C -45°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] Pin driver strength Figure 31-22. ATmega169A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 5V). 5.05 5.00 4.95 4.90 4.85 VOH [V] 31.1.8 4.80 4.75 -45°C 4.70 25°C 4.65 85°C 4.60 4.
Figure 31-23. Atmel ATmega169A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -45°C 2.2 25°C 2.1 85°C 2 0 2 4 6 8 10 IOH [mA] Figure 31-24. ATmega169A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.9 1.8 1.7 VOH [V] 1.6 1.5 -45°C 25°C 85°C 1.4 1.3 1.2 1.1 1.0 0 0.5 1 1.5 2 2.5 3 3.
Figure 31-25. Atmel ATmega169A: I/O pin output voltage vs. source current, port B (VCC= 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -45°C 4.5 25°C 4.4 85°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-26. ATmega169A: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -45°C 1.8 25°C 1.6 85°C 1.4 1.2 1.
Figure 31-27. Atmel ATmega169A: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.9 1.8 VOH [V] 1.7 1.6 1.5 -45°C 1.4 25°C 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 31-28. ATmega169A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 1.1 85°C 1.0 0.9 0.8 25°C VOL [V] 0.7 0.6 -45°C 0.5 0.4 0.3 0.2 0.
Figure 31-29. Atmel ATmega169A. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.1 85°C 1.0 0.9 0.8 25°C VOL [V] 0.7 0.6 -45°C 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-30. ATmega169A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). 0.5 85°C 0.4 25°C 0.3 VOL [V] -45°C 0.2 0.1 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
VOL [V] Figure 31-31. Atmel ATmega169A: I/O pin output voltage vs. sink current, port B (VCC = 5V). 0.6 85°C 0.5 25°C 0.4 -45°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-32. ATmega169A: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -45°C 0.4 0.
Figure 31-33. Atmel ATmega169A: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.5 85°C 0.4 25°C 0.3 VOL [V] -45°C 0.2 0.1 0 0 1 2 3 4 5 6 IOL [mA] Pin Threshold and Hysteresis Figure 31-34. ATmega169A: I/O pin input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.1 85°C 25°C -45°C 2.9 2.7 2.5 Threshold [V] 31.1.9 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-35. Atmel ATmega169A: I/O pin inputThreshold voltage vs. VCC (VIL, I/O pin read as “0”). 2.4 85°C 25°C -45°C 2.1 Threshold [V] 1.8 1.5 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-36. ATmega169A: I/O pin input Hysteresis vs. VCC. 0.65 -45°C 25°C 85°C Input Hysteresis [mV] 0.60 0.55 0.50 0.45 0.40 0.35 0.30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-37. Atmel ATmega169A: Reset input Threshold voltage vs. VCC (VIH, reset pin read as “1”). 2.5 -45°C 25°C 85°C 2.3 2.1 Threshold [V] 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-38. ATmega169A: Reset input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 2.4 85°C 25°C -45°C 2.2 2.0 Threshold [V] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-39. Atmel ATmega169A: Reset input pin Hysteresis vs. VCC. 0.7 0.6 Input Hysteresis [V] 0.5 0.4 0.3 0.2 -45°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] BOD Thresholds and Analog Comparator offset Figure 31-40. ATmega169A: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.37 Rising Vcc 4.35 4.33 BOD threshold [V] 31.1.10 4.31 Falling Vcc 4.29 4.27 4.25 4.
Figure 31-41. Atmel ATmega169A: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.767 Rising Vcc 2.752 BOD threshold [V] 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.662 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 75 85 Temperature [°C] Figure 31-42. ATmega169A: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.831 Rising Vcc 1.826 BOD threshold [V] 1.821 1.816 1.811 Falling Vcc 1.806 1.801 1.796 1.791 1.
Figure 31-43. Atmel ATmega169A: Bandgap voltage vs. VCC. 1.105 1.10 Bandgap voltage [V] 1.095 85°C 25°C 1.090 1.085 1.080 1.075 1.070 -45°C 1.065 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] Figure 31-44. ATmega169A: Bandgap voltage vs. temperature. 1.102 1.8V 2.7V 4.0V 5.5V Bandgap Voltage [V] 1.097 1.092 1.087 1.082 1.077 1.072 1.
Figure 31-45. Atmel ATmega169A: Analog Comparator offset voltage vs. Common mode voltage (VCC = 5V). Comparator Offset Voltage [V] 0.007 85°C 25°C 0.006 -40°C 0.005 0.004 0.003 0.002 0.001 0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 Common Mode Voltage [V] Comparator Offset Voltage [V] Figure 31-46. ATmega169A: Analog Comparator offset voltage vs. Common Mode voltage (VCC = 2.7V). CC 0.0030 85°C 0.0025 25°C -40°C 0.0020 0.0015 0.0010 0.0005 0 0 0.3 0.6 0.9 1.2 1.5 1.
Internal oscillator speed Figure 31-47. Atmel ATmega169A: Watchdog oscillator frequency vs. VCC. 1300 -45°C 25°C 85°C 1250 FRC [kHz] 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-48. ATmega169A: Watchdog oscillator frequency vs. temperature. 1300 1250 FRC [kHz] 31.1.11 5.5V 1200 5.0V 1150 4.5V 4.0V 3.0V 2.7V 1100 1.
Figure 31-49. Atmel ATmega169A: Calibrated 8MHz RC oscillator frequency vs. temperature. 5.5V 4.5V 3.3V 8.2 8.1 1.8V FRC [MHz] 8.0 7.9 7.8 7.7 7.6 7.5 -50 -30 -10 10 30 50 70 90 Temperature [°C] Figure 31-50. ATmega169A: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.2 85°C 8.1 25°C FRC [MHz] 8.0 7.9 7.8 -45°C 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-51. Atmel ATmega169A: Calibrated 8MHz RC oscillator frequency vs. Osccal value. 85°C 25°C -45°C 16 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] Current consumption of peripheral units Figure 31-52. ATmega169A: Brownout Detector current vs. VCC. 44 40 36 32 ICC [µA] 31.1.12 28 85°C 25°C -45°C 24 20 16 12 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-53. Atmel ATmega169A: Active supply current with ADC at 50kHz vs. VCC. 400 375 85°C 25°C -45°C 350 ICC [µA] 325 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-54. ATmega169A: Active supply current with ADC , p at 200kHz vs. VCC. 375 85°C -45°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-55. Atmel ATmega169A: Active supply current with ADC at 1MHz vs. VCC. 350 85°C 25°C -45°C 325 300 ICC [µA] 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-56. ATmega169A: AREF external reference current vs. VCC. 180 85°C 25°C -45°C 160 ICC [µA] 140 120 100 80 60 40 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-57. Atmel ATmega169A: Watchdog Timer current vs. VCC. 30 85°C 25°C -45°C 25 ICC [µA] 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-58. ATmega169A: Analog Comparator current vs. VCC. 85 -45°C 80 75 25°C 85°C 70 ICC [µA] 65 60 55 50 45 40 35 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-59. Atmel ATmega169A: Programming current vs. VCC. 16 14 -45°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Current consumption in Reset and Reset Pulswidth Figure 31-60. ATmega169A: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pullup. 0.16 5.5V 0.14 5.0V 0.12 4.5V 0.10 ICC [mA] 31.1.13 4.0V 0.08 3.3V 0.06 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-61. Atmel ATmega169A: Reset supply current vs. VCC (1 - 16MHz, excluding current through the reset pull-up). 2.1 5.5V 1.8 5.0V ICC [mA] 1.5 4.5V 1.2 4.0V 0.9 3.3V 0.6 2.7V 0.3 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency [MHz] Figure 31-62. ATmega169A: Minimum reset pulse width vs. VCC. 2400 Pulsewidth [ns] 2000 1600 1200 800 85°C 25°C -45°C 400 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.2 Atmel ATmega169PA 31.2.1 Active supply current Figure 31-63. ATmega169PA: Active supply current vs. frequency (0.1 - 1.0MHz). 1.2 5.5V 1.0 5.0V ICC [mA] 0.8 4.5V 4.0V 0.6 3.3V 0.4 2.7V 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-64. ATmega169PA: Active supply current vs. frequency (1 - 16MHz). 11 10 5.5V 9 5.0V 8 4.5V ICC [mA] 7 6 4.0V 5 4 3.3V 3 2.7V 2 1 1.
Figure 31-65. Atmel ATmega169PA: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 6 85°C 25°C -45°C 5 ICC [mA] 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-66. ATmega169PA: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 1.4 25°C 85°C -45°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-67. Atmel ATmega169PA: Active supply current vs. VCC (32kHz watch XTAL). 40 85°C 25°C -45°C 35 30 ICC [µA] 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-68. ATmega169PA: Idle supply current vs. frequency (0.1 - 1.0MHz). 0.25 5.5V 0.20 ICC [mA] 31.2.2 5.0V 4.5V 0.15 4.0V 3.3V 0.10 2.7V 0.05 1.8V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-69. Atmel ATmega169PA: Idle supply current vs. frequency (1 - 16MHz). 3.5 5.5V 3.0 5.0V 4.5V ICC [mA] 2.5 2.0 4.0V 1.5 3.3V 1.0 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency [MHz] Figure 31-70. ATmega169PA: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.00 25°C 85°C 1.75 -45°C 1.50 ICC [mA] 1.25 1.00 0.75 0.50 0.25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-71. Atmel ATmega169PA: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 0.40 85°C 25°C -45°C 0.35 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-72. ATmega169PA: Idle supply current vs. VCC (32kHz watch XTAL). 9 85°C 25°C -45°C 8 7 ICC [µA] 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.2.3 Atmel ATmega169PA: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-3. ATmega169PA: Additional current consumption for the different I/O modules (absolute values).
Power-down supply current Figure 31-73. Atmel ATmega169PA: Power-down supply current vs. VCC (Watchdog Timer disabled). 1.4 85°C 1.2 ICC [µA] 1.0 0.8 0.6 0.4 -45°C 25°C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-74. ATmega169PA: Power-down supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -45°C 18 16 14 ICC [µA] 31.2.4 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.2.5 Power-save supply current Figure 31-75. Atmel ATmega169PA: Power-save supply current vs. VCC (Watchdog Timer disabled). 2.0 85°C 1.8 1.6 ICC [µA] 1.4 1.2 25°C 1.0 -45°C 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby supply current Figure 31-76. ATmega169PA: Standby supply current vs. VCC (32kHz watch XTAL, Watchdog Timer disabled).
Figure 31-77. Atmel ATmega169PA: Standby supply current vs. VCC (XTAL and Resonator, Watchdog Timer disabled). g p p p g p p 0.18 6MHz_res 6MHz_xtal 0.16 4MHz_xtal 4MHz_res 0.14 ICC [mA] 0.12 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.10 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Pin pull-up Figure 31-78. ATmega169PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 150 125 100 IOP [µA] 31.2.7 75 50 25°C 85°C -45°C 25 0 0 0.5 1 1.5 2 2.5 3 3.
Figure 31-79. Atmel ATmega169PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 20 85°C 25°C -45°C 10 0 0 0.5 1 1.5 2 2.5 3 VOP [V] Figure 31-80. ATmega169PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 IOP [µA] 35 30 25 20 15 10 25°C 85°C -45°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 31-81. Atmel ATmega169PA: Reset pull-up resistor current vs. Reset pin voltage (VCC = 5V). 120 100 IRESET [µA] 80 60 40 25°C 85°C -45°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET [V] Figure 31-82. ATmega169PA: Reset pull-up resistor current vs. Reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C 85°C -45°C 10 0 0 0.5 1 1.5 2 2.
Figure 31-83. Atmel ATmega169PA: Reset pull-up resistor current vs. Reset pin voltage (VCC = 1.8V). 40 35 IRESET [µA] 30 25 20 15 10 25°C 85°C -45°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] Pin driver strength Figure 31-84. ATmega169PA: I/O pin output voltage vs. Source current, ports A, C, D, E, F, G (VCC = 5V). 5.05 5.00 4.95 4.90 4.85 VOH [V] 31.2.8 4.80 4.75 -45°C 4.70 25°C 4.65 85°C 4.60 4.
Figure 31-85. Atmel ATmega169PA: I/O pin output voltage vs. Source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -45°C 2.2 25°C 2.1 85°C 2 0 2 4 6 8 10 IOH [mA] Figure 31-86. ATmega169PA: I/O pin output voltage vs. Source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.9 1.8 1.7 VOH [V] 1.6 1.5 -45°C 25°C 85°C 1.4 1.3 1.2 1.1 1.0 0 0.5 1 1.5 2 2.5 3 3.
Figure 31-87. Atmel ATmega169PA: I/O pin output voltage vs. Source current, Port B (VCC = 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -45°C 4.5 25°C 4.4 85°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-88. ATmega169PA: I/O pin output voltage vs. Source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -45°C 1.8 25°C 1.6 85°C 1.4 1.2 1.
Figure 31-89. Atmel ATmega169PA: I/O pin output voltage vs. Source current, port B (VCC = 1.8V). 1.9 1.8 VOH [V] 1.7 1.6 1.5 -45°C 1.4 25°C 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 31-90. ATmega169PA: I/O pin output voltage vs. Sink current, ports A, C, D, E, F, G (VCC = 5V). 1.1 85°C 1.0 0.9 0.8 25°C VOL [V] 0.7 0.6 -45°C 0.5 0.4 0.3 0.2 0.
Figure 31-91. Atmel ATmega169PA. I/O pin output voltage vs. Sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.1 85°C 1.0 0.9 0.8 25°C VOL [V] 0.7 0.6 -45°C 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-92. ATmega169PA: I/O pin output voltage vs. Sink current, ports A, C, D, E, F, G (VCC = 1.8V). 0.5 85°C 0.4 25°C 0.3 VOL [V] -45°C 0.2 0.1 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
VOL [V] Figure 31-93. Atmel ATmega169PA: I/O pin output voltage vs. Sink current, port B (VCC = 5V). 0.6 85°C 0.5 25°C 0.4 -45°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-94. ATmega169PA: I/O pin output voltage vs. Sink current, port B (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -45°C 0.4 0.
Figure 31-95. Atmel ATmega169PA: I/O pin output voltage vs. Sink current, port B (VCC = 1.8V). 0.5 85°C 0.4 25°C 0.3 VOL [V] -45°C 0.2 0.1 0 0 1 2 3 4 5 6 IOL [mA] Pin Threshold and Hysteresis Figure 31-96. ATmega169PA: I/O pin Input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.1 85°C 25°C -45°C 2.9 2.7 2.5 Threshold [V] 31.2.9 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-97. Atmel ATmega169PA. I/O pin Input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 2.4 85°C 25°C -45°C 2.1 Threshold [V] 1.8 1.5 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-98. ATmega169PA: I/O pin Input Hysteresis vs. VCC. 0.65 -45°C 25°C 85°C Input Hysteresis [mV] 0.60 0.55 0.50 0.45 0.40 0.35 0.30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-99. Atmel ATmega169PA: Reset Input Threshold voltage vs. VCC (VIH, reset pin read as “1”). 2.5 -45°C 25°C 85°C 2.3 2.1 Threshold [V] 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-100.ATmega169PA: Reset Input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 2.4 85°C 25°C -45°C 2.2 2.0 Threshold [V] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-101.Atmel ATmega169PA: Reset input pin Hysteresis vs. VCC. 0.7 0.6 Input Hysteresis [V] 0.5 0.4 0.3 0.2 -45°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] BOD Thresholds and Analog Comparator offset Figure 31-102.ATmega169PA: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.37 Rising Vcc 4.35 4.33 BOD threshold [V] 31.2.10 4.31 Falling Vcc 4.29 4.27 4.25 4.
Figure 31-103.Atmel ATmega169PA: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.767 Rising Vcc 2.752 BOD threshold [V] 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.662 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-104.ATmega169PA: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.831 Rising Vcc 1.826 BOD threshold [V] 1.821 1.816 1.811 Falling Vcc 1.806 1.801 1.796 1.791 1.
Figure 31-105.Atmel ATmega169PA: Bandgap voltage vs. VCC. 1.105 1.10 Bandgap voltage [V] 1.095 85°C 25°C 1.090 1.085 1.080 1.075 1.070 -45°C 1.065 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] Figure 31-106.ATmega169PA: Bandgap voltage vs. temperature. 1.102 1.8V 2.7V 4.0V 5.5V Bandgap Voltage [V] 1.097 1.092 1.087 1.082 1.077 1.072 1.
Figure 31-107.Atmel ATmega169PA: Analog Comparator offset voltage vs. Common Mode voltage (VCC = 5V). Comparator Offset Voltage [V] 0.007 85°C 25°C 0.006 -40°C 0.005 0.004 0.003 0.002 0.001 0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 Common Mode Voltage [V] Comparator Offset Voltage [V] Figure 31-108.ATmega169PA: Analog Comparator offset voltage vs. Common Mode voltage (VCC = 2.7V). 0.0030 85°C 0.0025 25°C -40°C 0.0020 0.0015 0.0010 0.0005 0 0 0.3 0.6 0.9 1.2 1.5 1.
Internal oscillator speed Figure 31-109.Atmel ATmega169PA: Watchdog oscillator frequency vs. VCC. 1300 -45°C 25°C 85°C 1250 FRC [kHz] 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-110.ATmega169PA: Watchdog oscillator frequency vs. temperature. 1300 1250 FRC [kHz] 31.2.11 5.5V 1200 5.0V 1150 4.5V 4.0V 3.0V 2.7V 1100 1.
Figure 31-111.Atmel ATmega169PA: Calibrated 8MHz RC oscillator frequency vs. temperature. 5.5V 4.5V 3.3V 8.2 8.1 1.8V FRC [MHz] 8.0 7.9 7.8 7.7 7.6 7.5 -50 -30 -10 10 30 50 70 90 Temperature [°C] Figure 31-112.ATmega169PA: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.2 85°C 8.1 25°C FRC [MHz] 8.0 7.9 7.8 -45°C 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-113.Atmel ATmega169PA: Calibrated 8MHz RC oscillator frequency vs. Osccal value. 85°C 25°C -45°C 16 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] Current consumption of peripheral units Figure 31-114.ATmega169PA: Brownout Detector current vs. VCC. 44 40 36 32 ICC [µA] 31.2.12 28 85°C 25°C -45°C 24 20 16 12 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-115.Atmel ATmega169PA: Active supply current with ADC at 50kHz vs. VCC. 400 375 85°C 25°C -45°C 350 ICC [µA] 325 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-116.ATmega169PA: Active supply current with ADC at 200kHz vs. VCC. 375 85°C -45°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-117.Atmel ATmega169PA: Active supply current with ADC at 1MHz vs. VCC. 350 85°C 25°C -45°C 325 300 ICC [µA] 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-118.ATmega169PA: AREF external reference current vs. VCC. 180 85°C 25°C -45°C 160 ICC [µA] 140 120 100 80 60 40 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-119.Atmel ATmega169PA: Watchdog Timer current vs. VCC. 30 85°C 25°C -45°C 25 ICC [µA] 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-120.ATmega169PA: Analog Comparator current vs. VCC. 85 -45°C 80 75 25°C 85°C 70 ICC [µA] 65 60 55 50 45 40 35 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-121.Atmel ATmega169PA: Programming current vs. VCC. 16 14 -45°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Current consumption in Reset and Reset Pulswidth Figure 31-122.ATmega169PA: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pull-up). 0.16 5.5V 0.14 5.0V 0.12 4.5V 0.10 ICC [mA] 31.2.13 4.0V 0.08 3.3V 0.06 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-123.Atmel ATmega169PA: Reset supply current vs. VCC (1 - 16MHz, excluding current through the reset pull-up). 2.1 5.5V 1.8 5.0V ICC [mA] 1.5 4.5V 1.2 4.0V 0.9 3.3V 0.6 2.7V 0.3 1.8V 0 0 2 4 6 8 10 12 14 16 Frequency [MHz] Figure 31-124.ATmega169PA: Minimum reset pulse width vs. VCC. 2400 Pulsewidth [ns] 2000 1600 1200 800 85°C 25°C -45°C 400 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Active supply current Figure 31-125.ATmega329A: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.4 5.5V 1.2 5.0V 1.0 ICC [mA] 31.3.1 Atmel ATmega329A 4.5V 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-126.ATmega329A: Active supply current vs. frequency (1 - 20MHz). ICC [mA] 31.3 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
Figure 31-127.Atmel ATmega329A: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 7.0 85°C 25°C -40°C 6.5 6.0 5.5 ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-128.ATmega329A: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 1.6 85°C 1.4 25°C -40°C ICC [mA] 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ICC [mA] Figure 31-129.Atmel ATmega329A: Active supply current vs. VCC (32kHz watch XTAL). 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 85°C 25°C -40°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-130.ATmega329A: Idle supply current vs.low frequency (0.1 - 1.0MHz). 0.35 ICC [MHz] 31.3.2 0.30 5.5V 0.25 5.0V 4.5V 4.0V 3.3V 0.20 0.15 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-131.Atmel ATmega329A: Idle supply current vs. frequency (1 - 20MHz). 5.0 4.5 5.5V 4.0 5.0V ICC [MHz] 3.5 4.5V 4.5 3.0 2.5 4.0V 2.0 1.5 3.3V 1.0 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [V] Figure 31-132.ATmega329A: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.0 1.8 85°C 25°C 1.6 -40°C ICC [mA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-133.Atmel ATmega329A: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 0.50 85°C 25°C 0.45 0.40 -40°C ICC [mA] 0.35 0.30 0.25 0.20 0.15 0.10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-134.ATmega329A: Idle supply current vs. VCC (32kHz watch XTAL). 10 9 85°C 8 25°C -40°C ICC [mA] 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.3.3 Atmel ATmega329A: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-5. ATmega329A: Additional current consumption for the different I/O modules (absolute values).
Power-down supply current Figure 31-135.Atmel ATmega329A: Power-down supply current vs. VCC (Watchdog Timer disabled). 2.0 85°C 1.8 1.6 ICC [µA] 1.4 1.2 1.0 0.8 0.6 0.4 25°C -40°C 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC [V] Figure 31-136.ATmega329A: Power-down supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -40°C 18 16 14 ICC [µA] 31.3.4 12 10 8 6 4 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.
31.3.5 Power-save supply current Figure 31-137.Atmel ATmega329A: Power-save supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 25°C 1.1 -40°C 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby supply current Figure 31-138.ATmega329A Standby supply current vs.
Figure 31-139.Atmel ATmega329A: Standby supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.13 6MHz_xtal 6MHz_res 0.11 4MHz_xtal 4MHz_res ICC [mA] 0.09 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.07 0.05 0.03 0.01 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Pin pull-up Figure 31-140.ATmega329A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 160 140 120 100 IOP [µA] 31.3.7 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-141.Atmel ATmega329A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 90 80 70 IOP [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.5 1 1.5 2 2.5 3 VOP [V] Figure 31-142.ATmega329A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 60 50 IOP [µA] 40 30 20 10 -40°C 25°C 85°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 31-143.Atmel ATmega329A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 140 120 IRESET [µA] 100 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRESET [V] Figure 31-144.ATmega329A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 70 60 IRESET [µA] 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.
Figure 31-145.Atmel ATmega329A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 40 35 IRESET [µA] 30 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] Pin driver strength Figure 31-146.ATmega329A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 5V). 5.05 5.00 4.95 4.90 VOH [V] 31.3.8 4.85 4.80 4.75 -40°C 4.70 25°C 4.65 85°C 4.
Figure 31-147.Atmel ATmega329A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -40°C 2.2 25°C 2.1 85°C 2.0 1.9 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 31-148.ATmega329A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.9 1.8 VOH [V] 1.7 1.6 1.5 -40°C 1.4 25°C 85°C 1.3 1.2 0 0.5 1 1.5 2 2.5 3 3.
Figure 31-149.Atmel ATmega329A: I/O pin output voltage vs. source current, port B (VCC= 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-150.ATmega329A: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -40°C 1.8 25°C 1.6 85°C 1.4 1.
Figure 31-151.Atmel ATmega329A: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.8 1.7 VOH [V] 1.6 1.5 -40°C 25°C 1.4 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 31-152.ATmega329A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
Figure 31-153.Atmel ATmega329A. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-154.ATmega329A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). VOL [V] 0.35 0.30 85°C 0.25 25°C 0.20 -40°C 0.15 0.10 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 31-155.Atmel ATmega329A: I/O pin output voltage vs. sink current, port B (VCC = 5V). VOL [V] 0.7 0.6 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-156.ATmega329A: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C 1.0 25°C VOL [V] 0.8 -40°C 0.6 0.4 0.
Figure 31-157.Atmel ATmega329A: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.55 85°C 0.50 0.45 0.40 25°C VOL [V] 0.35 0.30 -40°C 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 IOL [mA] Pin Threshold and Hysteresis Figure 31-158.ATmega329A: I/O pin Input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.0 -40°C 25°C 85°C 2.7 2.4 Threshold [V] 31.3.9 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-159.Atmel ATmega329A. I/O pin Input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 85°C 25°C -40°C 2.5 2.2 Threshold [V] 1.9 1.6 1.3 1.0 0.7 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-160.ATmega329A: I/O pin Input Hysteresis vs. VCC. 0.57 -40°C 25°C 85°C 0.53 Input Hysteresis [mV] 0.49 0.45 0.41 0.37 0.33 0.29 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-161.Atmel ATmega329A: Reset input Threshold voltage vs. VCC (VIH, reset pin read as “1”). 2.4 25°C -40°C 2.2 85°C Threshold [V] 2.0 1.8 1.6 1.4 1.2 1.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-162.ATmega329A: Reset input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 2.50 -40°C 85°C 25°C 2.25 Threshold [V] 2.00 1.75 1.50 1.25 1.00 0.75 0.50 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-163.Atmel ATmega329A: Reset pin Input Hysteresis vs. VCC. 0.7 Input Hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] BOD Thresholds and Analog Comparator offset Figure 31-164.ATmega329A: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.350 Rising Vcc 4.325 BOD threshold [V] 31.3.10 4.300 Falling Vcc 4.275 4.250 4.
Figure 31-165.Atmel ATmega329A: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.775 Rising Vcc BOD threshold [V] 2.750 2.725 2.700 Falling Vcc 2.675 2.650 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 31-166.ATmega329A: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.835 Rising Vcc BOD threshold [V] 1.825 1.815 Falling Vcc 1.805 1.795 1.
Figure 31-167.Atmel ATmega329A: Bandgap voltage vs. VCC. 1.120 1.115 Bandgap Voltage [V] 1.110 25°C 1.105 1.100 85°C 1.095 1.090 1.085 -40°C 1.080 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] Figure 31-168.ATmega329A: Bandgap voltage vs. temperature. Bandgap Voltage [V] 1.115 1.110 1.8V 2.7V 4.0V 1.105 5.5V 1.100 1.095 1.090 1.
Internal oscillator speed Figure 31-169.Atmel ATmega329A: Watchdog oscillator frequency vs. VCC. 1225 1200 25°C -40°C 85°C 1175 FRC [kHz] 1150 1125 1100 1075 1050 1025 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-170.ATmega329A: Watchdog oscillator frequency vs. temperature. 1250 1200 5.5V FRC [kHz] 31.3.11 1150 5.0V 4.5V 4.0V 1100 3.0V 2.7V 1050 1.
Figure 31-171.Atmel ATmega329A: Calibrated 8MHz RC oscillator frequency vs. temperature. 8.3 5.5V 4.5V 3.3V 2.7V 1.8V 8.2 8.1 FRC [MHz] 8.0 7.9 7.8 7.7 7.6 7.5 7.4 -40 -20 0 20 40 60 80 Temperature [°C] Figure 31-172.ATmega329A: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.3 85°C 8.2 8.1 25°C FRC [MHz] 8.0 7.9 7.8 7.7 -40°C 7.6 7.5 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-173.Atmel ATmega329A: Calibrated 8MHz RC oscillator frequency vs. Osccal value. 16 85°C 25°C -40°C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] Current consumption of peripheral units Figure 31-174.ATmega329A: Brownout Detector current vs. VCC. 45 40 35 ICC [µA] 31.3.12 30 85°C 25°C -40°C 25 20 15 10 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-175.Atmel ATmega329A: Active supply current with ADC at 50kHz vs. VCC. 375 -40°C 85°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-176.ATmega329A: Active supply current with ADC at 200kHz vs. VCC. 375 350 85°C -40°C 25°C 325 ICC [µA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-177.Atmel ATmega329A: Active supply current with ADC at 1MHz vs. VCC. 375 -40°C 85°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-178.ATmega329A: AREF external reference current vs. VCC. 180 85°C 25°C -40°C 160 140 ICC [µA] 120 100 80 60 40 20 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-179.Atmel ATmega329A: Watchdog Timer current vs. VCC. 20.0 85°C 25°C -40°C 17.5 15.0 ICC [µA] 12.5 10.0 7.5 5.0 2.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-180.ATmega329A: Analog Comparator current vs. VCC. 90 -40°C 85°C 25°C 80 ICC [µA] 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-181.Atmel ATmega329A: Programming current vs. VCC. 14 -40°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Current consumption in Reset and Reset Pulswidth Figure 31-182.ATmega329A: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pullup). 0.16 0.14 ICC [mA] 31.3.13 5.5V 0.12 5.0V 0.10 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-183.Atmel ATmega329A: Reset supply current vs. VCC (1 - 20MHz, excluding current through the reset pull-up). 2.5 5.5V ICC [mA] 2.0 5.0V 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 31-184.ATmega329A: Minimum reset pulse width vs. VCC. 2500 2250 2000 Pulsewidth [ns] 1750 1500 1250 1000 750 85°C 25°C -40°C 500 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.4 Atmel ATmega329PA 31.4.1 Active supply current Figure 31-185.ATmega329PA: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.4 5.5V 1.2 5.0V ICC [mA] 1.0 4.5V 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] ICC [mA] Figure 31-186.ATmega329PA: Active supply current vs. frequency (1 - 20MHz). 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
Figure 31-187.Atmel ATmega329PA: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 7.0 85°C 25°C -40°C 6.5 6.0 5.5 ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-188.ATmega329PA: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 1.6 85°C 1.4 25°C -40°C ICC [mA] 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ICC [mA] Figure 31-189.Atmel ATmega329PA: Active supply current vs. VCC (32kHz watch XTAL). 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 85°C 25°C -40°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-190.ATmega329PA: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.35 ICC [MHz] 31.4.2 0.30 5.5V 0.25 5.0V 4.5V 4.0V 3.3V 0.20 0.15 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-191.Atmel ATmega329PA: Idle supply current vs. frequency (1 - 20MHz). 5.0 4.5 5.5V 4.0 5.0V ICC [MHz] 3.5 4.5V 4.5 3.0 2.5 4.0V 2.0 1.5 3.3V 1.0 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [V] Figure 31-192.ATmega329PA: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.0 1.8 85°C 25°C 1.6 -40°C ICC [mA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-193.Atmel ATmega329PA: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 0.50 85°C 25°C 0.45 0.40 -40°C ICC [mA] 0.35 0.30 0.25 0.20 0.15 0.10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-194.ATmega329PA: Idle supply current vs. VCC (32kHz watch XTAL). 10 9 85°C 8 25°C -40°C ICC [mA] 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.4.3 Atmel ATmega329PA: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-7. ATmega329PA: Additional current consumption for the different I/O modules (absolute values).
Power-down supply current Figure 31-195.Atmel ATmega329PA: Power-down supply current vs. VCC (Watchdog Timer disabled). 2.0 85°C 1.8 1.6 ICC [µA] 1.4 1.2 1.0 0.8 0.6 0.4 25°C -40°C 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC [V] Figure 31-196.ATmega329PA: Power-down supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -40°C 18 16 14 ICC [µA] 31.4.4 12 10 8 6 4 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.
31.4.5 Power-save supply current Figure 31-197.Atmel ATmega329PA: Power-save supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 25°C 1.1 -40°C 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby supply current Figure 31-198.ATmega329PA standby supply current vs.
Figure 31-199.Atmel ATmega329PA standby supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.13 6MHz_xtal 6MHz_res 0.11 4MHz_xtal 4MHz_res ICC [mA] 0.09 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.07 0.05 0.03 0.01 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Pin pull-up Figure 31-200.ATmega329PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 160 140 120 100 IOP [µA] 31.4.7 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-201.Atmel ATmega329PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 90 80 70 IOP [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.5 1 1.5 2 2.5 3 VOP [V] Figure 31-202.ATmega329PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 60 50 IOP [µA] 40 30 20 10 -40°C 25°C 85°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 31-203.Atmel ATmega329PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 140 120 IRESET [µA] 100 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRESET [V] Figure 31-204.ATmega329PA: Reset pull-up resistor current vs. reset pin voltage (VCC=2.7V). 70 60 IRESET [µA] 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.
Figure 31-205.Atmel ATmega329PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 40 35 IRESET [µA] 30 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] Pin driver strength Figure 31-206.ATmega329PA: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 5V). 5.05 5.00 4.95 4.90 VOH [V] 31.4.8 4.85 4.80 4.75 -40°C 4.70 25°C 4.65 85°C 4.
Figure 31-207.Atmel ATmega329PA: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -40°C 2.2 25°C 2.1 85°C 2.0 1.9 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 31-208.ATmega329PA: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.9 1.8 VOH [V] 1.7 1.6 1.5 -40°C 1.4 25°C 85°C 1.3 1.2 0 0.5 1 1.5 2 2.5 3 3.
Figure 31-209.Atmel ATmega329PA: I/O pin output voltage vs. source current, port B (VCC= 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-210.ATmega329PA: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -40°C 1.8 25°C 1.6 85°C 1.4 1.
Figure 31-211.Atmel ATmega329PA: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.8 1.7 VOH [V] 1.6 1.5 -40°C 25°C 1.4 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 31-212.ATmega329PA: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
Figure 31-213.Atmel ATmega329PA. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-214.ATmega329PA: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). VOL [V] 0.35 0.30 85°C 0.25 25°C 0.20 -40°C 0.15 0.10 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 31-215.Atmel ATmega329PA: I/O pin output voltage vs. sink current, port B (VCC = 5V). VOL [V] 0.7 0.6 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-216.ATmega329PA: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C 1.0 25°C VOL [V] 0.8 -40°C 0.6 0.4 0.
Figure 31-217.Atmel ATmega329PA: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.55 85°C 0.50 0.45 0.40 25°C VOL [V] 0.35 0.30 -40°C 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 IOL [mA] Pin Threshold and Hysteresis Figure 31-218.ATmega329PA: I/O pin Input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.0 -40°C 25°C 85°C 2.7 2.4 Threshold [V] 31.4.9 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-219.Atmel ATmega329PA. I/O pin Input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 85°C 25°C -40°C 2.5 2.2 Threshold [V] 1.9 1.6 1.3 1.0 0.7 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-220.ATmega329PA: I/O pin Input Hysteresis vs. VCC. 0.57 -40°C 25°C 85°C 0.53 Input Hysteresis [mV] 0.49 0.45 0.41 0.37 0.33 0.29 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-221.Atmel ATmega329PA: Reset Input Threshold voltage vs. VCC (VIH, reset pin read as “1”). 2.4 25°C -40°C 2.2 85°C Threshold [V] 2.0 1.8 1.6 1.4 1.2 1.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-222.ATmega329PA: Reset Input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 2.50 -40°C 85°C 25°C 2.25 Threshold [V] 2.00 1.75 1.50 1.25 1.00 0.75 0.50 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-223.Atmel ATmega329PA: Reset input pin Hysteresis vs. VCC. 0.7 Input Hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] BOD Thresholds and Analog Comparator offset Figure 31-224.ATmega329PA: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.350 Rising Vcc 4.325 BOD threshold [V] 31.4.10 4.300 Falling Vcc 4.275 4.250 4.
Figure 31-225.Atmel ATmega329PA: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.775 Rising Vcc BOD threshold [V] 2.750 2.725 2.700 Falling Vcc 2.675 2.650 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 31-226.ATmega329PA: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.835 Rising Vcc BOD threshold [V] 1.825 1.815 Falling Vcc 1.805 1.795 1.
Figure 31-227.Atmel ATmega329PA: Bandgap voltage vs. VCC. 1.120 1.115 Bandgap Voltage [V] 1.110 25°C 1.105 1.100 85°C 1.095 1.090 1.085 -40°C 1.080 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] Figure 31-228.ATmega329PA: Bandgap voltage vs. temperature. Bandgap Voltage [V] 1.115 1.110 1.8V 2.7V 4.0V 1.105 5.5V 1.100 1.095 1.090 1.
Internal oscillator speed Figure 31-229.Atmel ATmega329PA: Watchdog Oscillator frequency vs. VCC. 1225 1200 25°C -40°C 85°C 1175 FRC [kHz] 1150 1125 1100 1075 1050 1025 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-230.ATmega329PA: Watchdog Oscillator frequency vs. temperature. 1250 1200 5.5V FRC [kHz] 31.4.11 1150 5.0V 4.5V 4.0V 1100 3.0V 2.7V 1050 1.
Figure 31-231.Atmel ATmega329PA: Calibrated 8MHz RC oscillator frequency vs. temperature. 8.3 5.5V 4.5V 3.3V 2.7V 1.8V 8.2 8.1 FRC [MHz] 8.0 7.9 7.8 7.7 7.6 7.5 7.4 -40 -20 0 20 40 60 80 Temperature [°C] Figure 31-232.ATmega329PA: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.3 85°C 8.2 8.1 25°C FRC [MHz] 8.0 7.9 7.8 7.7 -40°C 7.6 7.5 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-233.Atmel ATmega329PA: Calibrated 8MHz RC oscillator frequency vs. Osccal value. 16 85°C 25°C -40°C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] Current consumption of peripheral units Figure 31-234.ATmega329PA: Brownout Detector current vs. VCC. 45 40 35 ICC [µA] 31.4.12 30 85°C 25°C -40°C 25 20 15 10 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-235.Atmel ATmega329PA: Active supply current with ADC at 50kHz vs. VCC. 375 -40°C 85°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-236.ATmega329PA: Active supply current with ADC at 200kHz vs. VCC. 375 350 85°C -40°C 25°C 325 ICC [µA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-237.Atmel ATmega329PA: Active supply current with ADC at 1MHz vs. VCC. 375 -40°C 85°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-238.ATmega329PA: AREF external reference current vs. VCC. 180 85°C 25°C -40°C 160 140 ICC [µA] 120 100 80 60 40 20 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-239.Atmel ATmega329PA: Watchdog Timer current vs. VCC. 20.0 85°C 25°C -40°C 17.5 15.0 ICC [µA] 12.5 10.0 7.5 5.0 2.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-240.ATmega329PA: Analog Comparator current vs. VCC. 90 -40°C 85°C 25°C 80 ICC [µA] 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-241.Atmel ATmega329PA: Programming current vs. VCC. 14 -40°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Current consumption in Reset and Reset Pulswidth Figure 31-242.ATmega329PA: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pull-up). 0.16 0.14 ICC [mA] 31.4.13 5.5V 0.12 5.0V 0.10 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-243.Atmel ATmega329PA: Reset supply current vs. VCC (1 - 20MHz, excluding current through the reset pull-up). 2.5 5.5V ICC [mA] 2.0 5.0V 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 31-244.ATmega329PA: Minimum reset pulse width vs. VCC. 2500 2250 2000 Pulsewidth [ns] 1750 1500 1250 1000 750 85°C 25°C -40°C 500 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.5 Atmel ATmega3290A 31.5.1 Active supply current Figure 31-245.ATmega3290A: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.4 5.5V 1.2 5.0V ICC [mA] 1.0 4.5V 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] ICC [mA] Figure 31-246.ATmega3290A: Active supply current vs. frequency (1 - 20MHz). 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
Figure 31-247.Atmel ATmega3290A: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 7.0 85°C 25°C -40°C 6.5 6.0 5.5 ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-248.ATmega3290A: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 1.6 85°C 1.4 25°C -40°C ICC [mA] 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ICC [mA] Figure 31-249.Atmel ATmega3290A: Active supply current vs. VCC (32kHz watch XTAL). 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 85°C 25°C -40°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-250.ATmega3290A: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.35 ICC [MHz] 31.5.2 0.30 5.5V 0.25 5.0V 4.5V 4.0V 3.3V 0.20 0.15 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-251.Atmel ATmega3290A: Idle supply current vs. frequency (1 - 20MHz). 5.0 4.5 5.5V 4.0 5.0V ICC [MHz] 3.5 4.5V 4.5 3.0 2.5 4.0V 2.0 1.5 3.3V 1.0 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [V] Figure 31-252.ATmega3290A: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.0 1.8 85°C 25°C 1.6 -40°C ICC [mA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-253.ATmega3290A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.50 85°C 25°C 0.45 0.40 -40°C ICC [mA] 0.35 0.30 0.25 0.20 0.15 0.10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-254.ATmega3290A: Idle supply current vs. VCC (32kHz watch XTAL). 10 9 85°C 8 25°C -40°C ICC [mA] 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.5.3 Atmel ATmega3290A: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-9. ATmega3290A: Additional current consumption for the different I/O modules (absolute values).
Power-down supply current Figure 31-255.Atmel ATmega3290A: Power-down supply current vs. VCC (Watchdog Timer disabled). 2.0 85°C 1.8 1.6 ICC [µA] 1.4 1.2 1.0 0.8 0.6 0.4 25°C -40°C 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC [V] Figure 31-256.ATmega3290A: Power-down supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -40°C 18 16 14 ICC [µA] 31.5.4 12 10 8 6 4 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.
31.5.5 Power-save supply current Figure 31-257.Atmel ATmega3290A: Power-save supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 25°C 1.1 -40°C 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby supply current Figure 31-258.ATmega3290A: Standby supply current vs.
Figure 31-259.Atmel ATmega3290A: Standby supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.13 6MHz_xtal 6MHz_res 0.11 4MHz_xtal 4MHz_res ICC [mA] 0.09 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.07 0.05 0.03 0.01 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Pin pull-up Figure 31-260.ATmega3290A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 160 140 120 100 IOP [µA] 31.5.7 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-261.Atmel ATmega3290A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 90 80 70 IOP [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.5 1 1.5 2 2.5 3 VOP [V] Figure 31-262.ATmega3290A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 60 50 IOP [µA] 40 30 20 10 -40°C 25°C 85°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 31-263.Atmel ATmega3290A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 140 120 IRESET [µA] 100 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRESET [V] Figure 31-264.ATmega3290A: Reset pull-up resistor current vs. reset pin voltage (VCC=2.7V). 70 60 IRESET [µA] 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.
Figure 31-265.Atmel ATmega3290A: Reset pull-up resistor current vs. reset pin voltage (VCC=1.8V). 40 35 IRESET [µA] 30 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] Pin driver strength Figure 31-266.ATmega3290A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 5V). 5.05 5.00 4.95 4.90 VOH [V] 31.5.8 4.85 4.80 4.75 -40°C 4.70 25°C 4.65 85°C 4.
Figure 31-267.Atmel ATmega3290A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -40°C 2.2 25°C 2.1 85°C 2.0 1.9 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 31-268.ATmega3290A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.9 1.8 VOH [V] 1.7 1.6 1.5 -40°C 1.4 25°C 85°C 1.3 1.2 0 0.5 1 1.5 2 2.5 3 3.
Figure 31-269.Atmel ATmega3290A: I/O pin output voltage vs. source current, port B (VCC= 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-270.ATmega3290A: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -40°C 1.8 25°C 1.6 85°C 1.4 1.
Figure 31-271.Atmel ATmega3290A: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.8 1.7 VOH [V] 1.6 1.5 -40°C 25°C 1.4 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 31-272.ATmega3290A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
Figure 31-273.Atmel ATmega3290A. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-274.ATmega3290A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). VOL [V] 0.35 0.30 85°C 0.25 25°C 0.20 -40°C 0.15 0.10 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 31-275.Atmel ATmega3290A: I/O pin output voltage vs. sink current, port B (VCC = 5V). VOL [V] 0.7 0.6 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-276.ATmega3290A: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C 1.0 25°C VOL [V] 0.8 -40°C 0.6 0.4 0.
Figure 31-277.Atmel ATmega3290A: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.55 85°C 0.50 0.45 0.40 25°C VOL [V] 0.35 0.30 -40°C 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 IOL [mA] Pin Threshold and Hysteresis Figure 31-278.ATmega3290A: I/O pin Input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.0 -40°C 25°C 85°C 2.7 2.4 Threshold [V] 31.5.9 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-279.Atmel ATmega3290A: I/O pin Input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 85°C 25°C -40°C 2.5 2.2 Threshold [V] 1.9 1.6 1.3 1.0 0.7 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-280.ATmega3290A: I/O pin Input Hysteresis vs. VCC. 0.57 -40°C 25°C 85°C 0.53 Input Hysteresis [mV] 0.49 0.45 0.41 0.37 0.33 0.29 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-281.Atmel ATmega3290A: Reset Input Threshold voltage vs. VCC (VIH, reset pin read as “1”). 2.4 25°C -40°C 2.2 85°C Threshold [V] 2.0 1.8 1.6 1.4 1.2 1.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-282.ATmega3290A: Reset Input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 2.50 -40°C 85°C 25°C 2.25 Threshold [V] 2.00 1.75 1.50 1.25 1.00 0.75 0.50 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-283.Atmel ATmega3290A: Reset input pin Hysteresis vs. VCC. 0.7 Input Hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] BOD Thresholds and Analog Comparator offset Figure 31-284.ATmega3290A: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.350 Rising Vcc 4.325 BOD threshold [V] 31.5.10 4.300 Falling Vcc 4.275 4.250 4.
Figure 31-285.Atmel ATmega3290A: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.775 Rising Vcc BOD threshold [V] 2.750 2.725 2.700 Falling Vcc 2.675 2.650 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 31-286.ATmega3290A: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.835 Rising Vcc BOD threshold [V] 1.825 1.815 Falling Vcc 1.805 1.795 1.
Figure 31-287.Atmel ATmega3290A: Bandgap voltage vs. VCC. 1.120 1.115 Bandgap Voltage [V] 1.110 25°C 1.105 1.100 85°C 1.095 1.090 1.085 -40°C 1.080 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] Figure 31-288.ATmega3290A: Bandgap voltage vs. temperature. Bandgap Voltage [V] 1.115 1.110 1.8V 2.7V 4.0V 1.105 5.5V 1.100 1.095 1.090 1.
Internal oscillator speed Figure 31-289.Atmel ATmega3290A: Watchdog Oscillator frequency vs. VCC. 1225 1200 25°C -40°C 85°C 1175 FRC [kHz] 1150 1125 1100 1075 1050 1025 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-290.ATmega3290A: Watchdog Oscillator frequency vs. temperature. 1250 1200 5.5V FRC [kHz] 31.5.11 1150 5.0V 4.5V 4.0V 1100 3.0V 2.7V 1050 1.
Figure 31-291.Atmel ATmega3290A: Calibrated 8MHz RC oscillator frequency vs. temperature. 8.3 5.5V 4.5V 3.3V 2.7V 1.8V 8.2 8.1 FRC [MHz] 8.0 7.9 7.8 7.7 7.6 7.5 7.4 -40 -20 0 20 40 60 80 Temperature [°C] Figure 31-292.ATmega3290A: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.3 85°C 8.2 8.1 25°C FRC [MHz] 8.0 7.9 7.8 7.7 -40°C 7.6 7.5 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-293.Atmel ATmega3290A: Calibrated 8MHz RC oscillator frequency vs. Osccal value. 16 85°C 25°C -40°C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] Current consumption of peripheral units Figure 31-294.ATmega3290A: Brownout Detector current vs. VCC. 45 40 35 ICC [µA] 31.5.12 30 85°C 25°C -40°C 25 20 15 10 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-295.Atmel ATmega3290A: Active supply current with ADC at 50kHz vs. VCC. 375 -40°C 85°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-296.ATmega3290A: Active supply current with ADC at 200kHz vs. VCC. 375 350 85°C -40°C 25°C 325 ICC [µA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-297.Atmel ATmega3290A: Active supply current with ADC at 1MHz vs. VCC. 375 -40°C 85°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-298.ATmega3290A: AREF external reference current vs. VCC. 180 85°C 25°C -40°C 160 140 ICC [µA] 120 100 80 60 40 20 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-299.Atmel ATmega3290A: Watchdog Timer current vs. VCC. 20.0 85°C 25°C -40°C 17.5 15.0 ICC [µA] 12.5 10.0 7.5 5.0 2.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-300.ATmega3290A: Analog Comparator current vs. VCC. 90 -40°C 85°C 25°C 80 ICC [µA] 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-301.Atmel ATmega3290A: Programming current vs. VCC. 14 -40°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Current consumption in Reset and Reset Pulswidth Figure 31-302.ATmega3290A: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pull-up). 0.16 0.14 ICC [mA] 31.5.13 5.5V 0.12 5.0V 0.10 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-303.Atmel ATmega3290A: Reset supply current vs. VCC (1 - 20MHz, excluding current through the reset pull-up). 2.5 5.5V ICC [mA] 2.0 5.0V 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 31-304.ATmega3290A: Minimum reset pulse width vs. VCC. 2500 2250 2000 Pulsewidth [ns] 1750 1500 1250 1000 750 85°C 25°C -40°C 500 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.6 Atmel ATmega3290PA 31.6.1 Active supply current Figure 31-305.ATmega3290PA: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.4 5.5V 1.2 5.0V ICC [mA] 1.0 4.5V 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] ICC [mA] Figure 31-306.ATmega3290PA: Active supply current vs. frequency (1 - 20MHz). 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
Figure 31-307.Atmel ATmega3290PA: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 7.0 85°C 25°C -40°C 6.5 6.0 5.5 ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-308.ATmega3290PA: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 1.6 85°C 1.4 25°C -40°C ICC [mA] 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ICC [mA] Figure 31-309.Atmel ATmega3290PA: Active supply current vs. VCC (32kHz watch XTAL). 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 85°C 25°C -40°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-310.ATmega3290PA: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.35 ICC [MHz] 31.6.2 0.30 5.5V 0.25 5.0V 4.5V 4.0V 3.3V 0.20 0.15 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-311.Atmel ATmega3290PA: Idle supply current vs. frequency (1 - 20MHz). 5.0 4.5 5.5V 4.0 5.0V ICC [MHz] 3.5 4.5V 4.5 3.0 2.5 4.0V 2.0 1.5 3.3V 1.0 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [V] Figure 31-312.ATmega3290PA: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.0 1.8 85°C 25°C 1.6 -40°C ICC [mA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-313.Atmel ATmega3290PA: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 0.50 85°C 25°C 0.45 0.40 -40°C ICC [mA] 0.35 0.30 0.25 0.20 0.15 0.10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-314.ATmega3290PA: Idle supply current vs. VCC (32kHz watch XTAL). 10 9 85°C 8 25°C -40°C ICC [mA] 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.6.3 Atmel ATmega3290PA: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-11. ATmega3290PA: Additional current consumption for the different I/O modules (absolute values).
Power-down supply current Figure 31-315.Atmel ATmega3290PA Power-down Supply current vs. VCC (Watchdog Timer disabled). 2.0 85°C 1.8 1.6 ICC [µA] 1.4 1.2 1.0 0.8 0.6 0.4 25°C -40°C 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC [V] Figure 31-316.ATmega3290PA: Power-down Supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -40°C 18 16 14 ICC [µA] 31.6.4 12 10 8 6 4 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.
Power-save supply current Figure 31-317.Atmel ATmega3290PA: Power-save Supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 85°C 2.1 1.9 1.7 ICC [mA] 31.6.5 1.5 1.3 25°C 1.1 -40°C 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2.
Standby supply current Figure 31-318.Atmel ATmega3290PA Standby Supply current vs. VCC (32kHz watch XTAL, Watchdog Timer disabled). 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 1.1 25°C 0.9 -40°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-319.ATmega3290PA: Standby Supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.13 6MHz_xtal 6MHz_res 0.11 4MHz_xtal 4MHz_res 0.09 ICC [mA] 31.6.6 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.07 0.05 0.03 0.01 1.5 2 2.5 3 3.
Pin pull-up Figure 31-320.Atmel ATmega3290PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 160 140 120 IOP [µA] 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VOP [V] Figure 31-321.ATmega3290PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 90 80 70 60 IOP [µA] 31.6.7 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.5 1 1.5 2 2.
Figure 31-322.Atmel ATmega3290PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 60 50 IOP [µA] 40 30 20 10 -40°C 25°C 85°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP [V] Figure 31-323.ATmega3290PA: Reset pull-up resistor current vs. reset pin voltage (VCC=5V). 140 120 IRESET [µA] 100 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
Figure 31-324.Atmel ATmega3290PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 70 60 IRESET [µA] 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 VRESET [V] Figure 31-325.ATmega3290PA: Reset pull-up resistor current vs. reset pin voltage (VCC=1.8V). 40 35 IRESET [µA] 30 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin driver strength Figure 31-326.Atmel ATmega3290PA: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 5V). 5.05 5.00 4.95 VOH [V] 4.90 4.85 4.80 4.75 -40°C 4.70 4.65 25°C 4.60 85°C 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 31-327.ATmega3290PA: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.8 2.7 2.6 2.5 VOH [V] 31.6.8 2.4 2.3 -40°C 2.2 25°C 2.1 85°C 2.0 1.
Figure 31-328.Atmel ATmega3290PA: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.9 1.8 VOH [V] 1.7 1.6 1.5 -40°C 1.4 25°C 85°C 1.3 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 31-329.ATmega3290PA: I/O pin output voltage vs. source current, port B (VCC= 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
Figure 31-330.Atmel ATmega3290PA: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -40°C 1.8 25°C 1.6 85°C 1.4 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-331.ATmega3290PA: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.8 1.7 VOH [V] 1.6 1.5 -40°C 25°C 1.4 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-332.Atmel ATmega3290PA: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-333.ATmega3290PA. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -40°C 0.4 0.
Figure 31-334.Atmel ATmega3290PA: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). VOL [V] 0.35 0.30 85°C 0.25 25°C 0.20 -40°C 0.15 0.10 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 31-335.ATmega3290PA: I/O pin output voltage vs. sink current, port B (VCC = 5V). VOL [V] 0.7 0.6 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.
Figure 31-336.Atmel ATmega3290PA: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C 1.0 25°C VOL [V] 0.8 -40°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-337.ATmega3290PA: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.55 85°C 0.50 0.45 0.40 25°C VOL [V] 0.35 0.30 -40°C 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Pin Threshold and Hysteresis Figure 31-338.Atmel ATmega3290PA: I/O pin Input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.0 -40°C 25°C 85°C 2.7 Threshold [V] 2.4 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-339.ATmega3290PA. I/O pin Input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 85°C 25°C -40°C 2.5 2.2 1.9 Threshold [V] 31.6.9 1.6 1.3 1.0 0.7 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-340.Atmel ATmega3290PA: I/O pin Input Hysteresis vs. VCC. 0.57 -40°C 25°C 85°C 0.53 Input Hysteresis [mV] 0.49 0.45 0.41 0.37 0.33 0.29 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-341.ATmega3290PA: Reset Input Threshold voltage vs. VCC (VIH, reset pin read as “1”). 2.4 25°C -40°C 2.2 85°C Threshold [V] 2.0 1.8 1.6 1.4 1.2 1.0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-342.Atmel ATmega3290PA: Reset Input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 2.50 -40°C 85°C 25°C 2.25 Threshold [V] 2.00 1.75 1.50 1.25 1.00 0.75 0.50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-343.ATmega3290PA: Reset input pin Hysteresis vs. VCC. 0.7 Input Hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator offset Figure 31-344.Atmel ATmega3290PA: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.350 Rising Vcc BOD threshold [V] 4.325 4.300 Falling Vcc 4.275 4.250 4.225 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 31-345.ATmega3290PA: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.775 Rising Vcc 2.750 BOD threshold [V] 31.6.10 2.725 2.700 Falling Vcc 2.675 2.
Figure 31-346.Atmel ATmega3290PA: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.835 Rising Vcc BOD threshold [V] 1.825 1.815 Falling Vcc 1.805 1.795 1.785 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 31-347.ATmega3290PA: Bandgap voltage vs. VCC. 1.120 1.115 Bandgap Voltage [V] 1.110 25°C 1.105 1.100 85°C 1.095 1.090 1.085 -40°C 1.080 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-348.Atmel ATmega3290PA: Bandgap voltage vs. temperature. Bandgap Voltage [V] 1.115 1.110 1.8V 2.7V 4.0V 1.105 5.5V 1.100 1.095 1.090 1.085 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Internal oscillator speed Figure 31-349.ATmega3290PA: Watchdog Oscillator frequency vs. VCC. 1225 1200 25°C -40°C 85°C 1175 1150 FRC [kHz] 31.6.11 1125 1100 1075 1050 1025 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-350.Atmel ATmega3290PA: Watchdog Oscillator frequency vs. temperature. 1250 1200 FRC [kHz] 5.5V 1150 5.0V 4.5V 4.0V 1100 3.0V 2.7V 1050 1.8V 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 31-351.ATmega3290PA: Calibrated 8MHz RC oscillator frequency vs. temperature. 8.3 5.5V 4.5V 3.3V 2.7V 1.8V 8.2 8.1 FRC [MHz] 8.0 7.9 7.8 7.7 7.6 7.5 7.
Figure 31-352.Atmel ATmega3290PA: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.3 85°C 8.2 8.1 25°C FRC [MHz] 8.0 7.9 7.8 7.7 -40°C 7.6 7.5 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-353.ATmega3290PA: Calibrated 8MHz RC oscillator frequency vs. Osccal value.
Current consumption of peripheral units Figure 31-354.Atmel ATmega3290PA: Brownout detector current vs. VCC. 45 40 ICC [µA] 35 30 85°C 25°C -40°C 25 20 15 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-355.ATmega3290PA: Active supply current with ADC at 50kHz vs. VCC. 375 -40°C 85°C 25°C 350 325 300 ICC [µA] 31.6.12 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-356.Atmel ATmega3290PA: Active supply current with ADC at 200kHz vs. VCC. 375 350 85°C -40°C 25°C 325 ICC [µA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-357.ATmega3290PA: Active supply current with ADC at 1MHz vs. VCC. 375 -40°C 85°C 25°C 350 325 ICC [µA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-358.Atmel ATmega3290PA: AREF external reference current vs. VCC. 180 85°C 25°C -40°C 160 140 ICC [µA] 120 100 80 60 40 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-359.ATmega3290PA: Watchdog Timer current vs. VCC. 20.0 85°C 25°C -40°C 17.5 15.0 ICC [µA] 12.5 10.0 7.5 5.0 2.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-360.Atmel ATmega3290PA: Analog Comparator current vs. VCC. 90 -40°C 85°C 25°C 80 ICC [µA] 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-361.ATmega3290PA: Programming current vs. VCC. 14 -40°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current consumption in Reset and Reset Pulswidth Figure 31-362.Atmel ATmega3290PA: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pull-up). 0.16 ICC [mA] 0.14 5.5V 0.12 5.0V 0.10 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-363.ATmega3290PA: Reset supply current vs. VCC (1 - 20MHz, excluding current through the reset pullup). 2.5 5.5V 2.0 ICC [mA] 31.6.13 5.0V 4.5V 1.5 4.0V 1.
Figure 31-364.Atmel ATmega3290PA: Minimum reset pulse width vs. VCC. 2500 2250 2000 Pulsewidth [ns] 1750 1500 1250 1000 750 85°C 25°C -40°C 500 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Active supply current Figure 31-365.ATmega649A: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.2 5.5V 5.0V 1.0 4.5V 0.8 4.0V ICC [mA] 31.7.1 Atmel ATmega649A 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-366.ATmega649A: Active supply current vs. frequency (1 - 20MHz). 16 5.5V 14 5.0V 12 4.5V 10 ICC [mA] 31.7 8 4.0V 6 3.3V 4 2.7V 2 1.
Figure 31-367.Atmel ATmega649A: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 7 85°C 25°C -45°C 6 ICC [mA] 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-368.ATmega649A: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 0.45 25°C 85°C -45°C 0.40 ICC [mA] 0.35 0.30 0.25 0.20 0.15 0.10 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-369.Atmel ATmega649A: Active supply current vs. VCC (32kHz watch XTAL). 85°C 25°C -45°C 40 36 32 ICC [mA] 28 24 20 16 12 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-370.ATmega649A: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.30 5.5V 0.27 5.0V 4.5V 0.24 0.21 ICC [mA] 31.7.2 0.18 4.0V 0.15 3.3V 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-371.Atmel ATmega649A: Idle supply current vs. frequency (1 - 20MHz). 16 5.5V 14 5.0V 12 4.5V ICC [mA] 10 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 31-372.ATmega649A: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.0 85°C 25°C -45°C 1.8 1.6 ICC [mA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-373.Atmel ATmega649A: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 1.4 85°C 25°C -45°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-374.ATmega649A: Idle supply current vs. VCC (32kHz watch XTAL). 9.5 85°C 8.5 25°C -45°C 7.5 ICC [mA] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.7.3 Atmel ATmega649A: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-13. Additional current consumption for the different I/O modules (absolute values).
Power-down supply current Figure 31-375.Atmel ATmega649A: Power-down supply current vs. VCC (Watchdog Timer disabled). 2.4 85°C 2.2 2.0 1.8 ICC [µA] 1.6 1.4 1.2 1.0 0.8 25°C -45°C 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-376.ATmega649A: Power-down supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -45°C 18 16 14 ICC [µA] 31.7.4 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-377.Atmel ATmega649A: Power-down supply current vs. VCC (32kHz watch XTAL). 1.5 85°C 1.3 ICC [mA] 1.1 0.9 0.7 0.5 0.3 25°C -45°C 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Power-save supply current Figure 31-378.ATmega649A: Power-save supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 2.5 85°C 2.3 2.1 1.9 ICC [mA] 31.7.5 1.7 1.5 1.3 1.1 25°C 0.9 -45°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Standby supply current Figure 31-379.Atmel ATmega649A standby supply current vs. VCC (32kHz watch XTAL, Watchdog Timer disabled). 2.5 85°C 2.3 2.1 ICC [mA] 1.9 1.7 1.5 1.3 1.1 25°C 0.9 -45°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-380.ATmega649A: Standby supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.125 6MHz_res 6MHz_xtal 0.115 0.105 4MHz_xtal 4MHz_res 0.095 0.085 ICC [mA] 31.7.6 0.075 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.065 0.055 0.
Pin pull-up Figure 31-381.Atmel ATmega649A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 160 140 120 IOP [µA] 100 80 60 40 25°C 85°C -45°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] Figure 31-382.ATmega649A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 50 IOP [µA] 31.7.7 40 30 20 10 25°C 0 85°C -45°C 0 0.5 1 1.5 2 2.
Figure 31-383.Atmel ATmega649A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 35 IOP [µA] 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25°C 85°C -45°C 1.8 VOP [V] Figure 31-384.ATmega649A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 120 105 IRESET [µA] 90 75 60 45 30 25°C -45°C 85°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-385.Atmel ATmega649A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 54 48 IRESET [µA] 42 36 30 24 18 12 25°C -45°C 85°C 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET [V] Figure 31-386.ATmega649A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 40 35 IRESET [µA] 30 25 20 15 10 25°C -45°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin driver strength Figure 31-387.Atmel ATmega649A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 5V). 5.00 4.95 4.90 VOH [V] 4.85 4.80 4.75 -45°C 4.70 4.65 25°C 4.60 85°C 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 31-388.ATmega649A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.7 2.6 2.5 2.4 VOH [V] 31.7.8 2.3 -45°C 2.2 2.1 25°C 2.0 85°C 1.
Figure 31-389.Atmel ATmega649A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.8 1.7 VOH [V] 1.6 1.5 -45°C 1.4 25°C 1.3 85°C 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 31-390.ATmega649A: I/O pin output voltage vs. source current, port B (VCC= 5V). 5.0 4.9 VOH [V] 4.8 4.7 4.6 -45°C 4.5 25°C 85°C 4.4 4.
Figure 31-391.Atmel ATmega649A: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -45°C 1.8 25°C 1.6 1.4 85°C 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-392.ATmega649A: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.80 1.75 1.70 1.65 VOH [V] 1.60 1.55 1.50 -45°C 1.45 1.40 25°C 85°C 1.35 1.30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-393.Atmel ATmega649A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 0.6 85°C 0.5 25°C 0.4 VOL [V] -45°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-394.ATmega649A. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -45°C 0.4 0.
Figure 31-395.Atmel ATmega649A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). 0.32 85°C 25°C 0.28 0.24 -45°C VOL [V] 0.20 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 31-396.ATmega649A: I/O pin output voltage vs. sink current, port B (VCC = 5V). 0.6 85°C 25°C 0.5 -45°C VOL [V] 0.4 0.3 0.2 0.
Figure 31-397.Atmel ATmega649A: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C 1.0 25°C VOL [V] 0.8 -45°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-398.ATmega649A: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.50 85°C 0.45 25°C 0.40 0.35 -45°C VOL [V] 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Pin Threshold and Hysteresis Figure 31-399.Atmel ATmega649A: I/O pin Input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.1 85°C 25°C -45°C 2.9 2.7 Threshold [V] 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-400.ATmega649A: I/O pin Input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 2.4 85°C 25°C -45°C 2.2 2.0 1.8 Threshold [V] 31.7.9 1.6 1.4 1.2 1.0 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-401.Atmel ATmega649A: I/O pin input Hysteresis vs. VCC. 0.60 -45°C 0.55 Input Hysteresis [V] -45°C 0.50 25°C 0.45 0.40 85°C 0.35 0.30 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-402.ATmega649A: Reset input Threshold voltage vs. VCC (VIH, reset pin read as “1”). -45°C 25°C 85°C 2.4 2.2 Threshold [V] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-403.Atmel ATmega649A: Reset input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 85°C 25°C -45°C 2.4 2.2 2.0 Threshold [V] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-404.ATmega649A: Reset input pin Hysteresis vs. VCC. 0.7 Input Hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -45°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator offset Figure 31-405.Atmel ATmega649A: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.41 Rising Vcc BOD threshold [V] 4.39 4.37 4.35 Falling Vcc 4.33 4.31 4.29 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 75 85 Temperature [°C] Figure 31-406.ATmega649A: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.795 2.785 Rising Vcc 2.775 2.765 BOD threshold [V] 31.7.10 2.755 2.745 2.735 Falling Vcc 2.725 2.715 2.705 2.695 2.
Figure 31-407.Atmel ATmega649A: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.845 Rising Vcc 1.840 BOD threshold [V] 1.835 1.830 1.825 Falling Vcc 1.820 1.815 1.810 1.805 1.800 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-408.ATmega649A: Bandgap voltage vs. VCC. 1.103 1.101 Bandgap Voltage [V] 1.099 25°C 1.097 85°C 1.095 1.093 1.091 1.089 1.087 1.085 -45°C 1.083 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-409.Atmel ATmega649A: Bandgap voltage vs. temperature. 1.110 1.8V 1.108 3.3V Bandgap Voltage [V] 1.106 5.0V 1.104 5.5V 1.102 1.100 1.098 1.096 1.094 1.092 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Internal oscillator speed Figure 31-410.ATmega649A: Watchdog Oscillator frequency vs. VCC. 1290 -45°C 25°C 1260 85°C 1230 1200 FRC [kHz] 31.7.11 1170 1140 1110 1080 1050 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-411.Atmel ATmega649A: Watchdog Oscillator frequency vs. temperature. 1290 1260 5.5V 1230 5.0V FRC [kHz] 1200 4.5V 4.0V 3.3V 2.7V 1170 1140 1110 1080 1.8V 1050 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-412.ATmega649A: Calibrated 8MHz RC oscillator frequency vs. temperature. 5.5V 4.0V 3.3V 2.7V 8.2 8.1 8.0 FRC [MHz] 7.9 1.8V 7.8 7.7 7.6 7.5 7.4 7.
Figure 31-413.Atmel ATmega649A: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.2 85°C 8.1 25°C 8.0 FRC [MHz] 7.9 -45°C 7.8 7.7 7.6 7.5 7.4 7.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-414.ATmega649A: Calibrated 8MHz RC oscillator frequency vs. Osccal value.
Current consumption of peripheral units Figure 31-415.Atmel ATmega649A: Brownout Detector current vs. VCC. 42 39 36 33 ICC [µA] 30 27 85°C 25°C -45°C 24 21 18 15 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-416.ATmega649A: Active supply current with ADC at 50kHz vs. VCC. 85°C 25°C -45°C 330 300 270 ICC [µA] 31.7.12 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-417.Atmel ATmega649A: Active supply current with ADC at 200kHz vs. VCC. 360 85°C 25°C -45°C 330 300 ICC [µA] 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-418.ATmega649A: Active supply current with ADC at 1MHz vs. VCC. 340 85°C 25°C -45°C 310 ICC [µA] 280 250 220 190 160 130 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-419.Atmel ATmega649A: AREF external reference current vs. VCC. 170 85°C 25°C -45°C 155 140 ICC [µA] 125 110 95 80 65 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-420.ATmega649A: Watchdog Timer current vs. VCC. 18 85°C 25°C -45°C 16 14 ICC [µA] 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-421.Atmel ATmega649A: Analog Comparator current vs. VCC. 110 25°C 100 85°C 90 ICC [µA] 80 -45°C 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-422.ATmega649A: Programming current vs. VCC. 20 -45°C 18 16 ICC [mA] 14 25°C 12 10 85°C 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current consumption in Reset and Reset Pulswidth Figure 31-423.Atmel ATmega649A: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pull-up). ICC [mA] 0.16 0.14 5.5V 0.12 5.0V 0.10 4.5V 4.0V 0.08 3.3V 0.06 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-424.ATmega649A: Reset supply current vs. VCC (1 - 20MHz, excluding current through the reset pullup). 2.4 5.5V 2.1 5.0V 1.8 4.5V 1.5 ICC [mA] 31.7.13 1.2 4.
Figure 31-425.Atmel ATmega649A: Minimum reset pulse width vs. VCC. 2400 2100 Pulsewidth [ns] 1800 1500 1200 900 600 85°C 25°C -45°C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Active supply current Figure 31-426.ATmega649P: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.2 5.5V 5.0V 1.0 4.5V 0.8 4.0V ICC [mA] 31.8.1 Atmel ATmega649P 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-427.ATmega649P: Active supply current vs. frequency (1 - 20MHz). 16 5.5V 14 5.0V 12 4.5V 10 ICC [mA] 31.8 8 4.0V 6 3.3V 4 2.7V 2 1.
Figure 31-428.Atmel ATmega649P: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 7 85°C 25°C -45°C 6 ICC [mA] 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-429.ATmega649P: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 1.4 85°C 25°C -45°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-430.Atmel ATmega649P: Active supply current vs. VCC (32kHz watch XTAL). 85°C 25°C -45°C 40 36 32 ICC [mA] 28 24 20 16 12 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-431.ATmega649P: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.30 5.5V 0.27 5.0V 4.5V 0.24 0.21 ICC [mA] 31.8.2 0.18 4.0V 0.15 3.3V 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-432.Atmel ATmega649P: Idle supply current vs. frequency (1 - 20MHz). 4.5 5.5V 4.0 5.0V 3.5 4.5V ICC [mA] 3.0 2.5 2.0 4.0V 1.5 3.3V 1.0 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 31-433.ATmega649P: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.0 85°C 25°C -45°C 1.8 1.6 ICC [mA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-434.Atmel ATmega649P: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 0.45 25°C 85°C -45°C 0.40 ICC [mA] 0.35 0.30 0.25 0.20 0.15 0.10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-435.ATmega649P: Idle supply current vs. VCC (32kHz watch XTAL). 9.5 85°C 8.5 25°C -45°C 7.5 ICC [mA] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.8.3 Atmel ATmega649P: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-15. Additional current consumption for the different I/O modules (absolute values).
Power-down supply current Figure 31-436.Atmel ATmega649P: Power-down supply current vs. VCC (Watchdog Timer disabled). 2.4 85°C 2.2 2.0 1.8 ICC [µA] 1.6 1.4 1.2 1.0 0.8 25°C -45°C 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-437.ATmega649P: Power-down supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -45°C 18 16 14 ICC [µA] 31.8.4 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-438.Atmel ATmega649P: Power-down supply current vs. VCC (32kHz watch XTAL). 1.5 85°C 1.3 ICC [mA] 1.1 0.9 0.7 0.5 0.3 25°C -45°C 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Power-save supply current Figure 31-439.ATmega649P: Power-save supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 2.5 85°C 2.3 2.1 1.9 ICC [mA] 31.8.5 1.7 1.5 1.3 1.1 25°C 0.9 -45°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Standby supply current Figure 31-440.Atmel ATmega649P standby supply current vs. VCC (32kHz watch XTAL, Watchdog Timer disabled). 2.5 85°C 2.3 2.1 ICC [mA] 1.9 1.7 1.5 1.3 1.1 25°C 0.9 -45°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-441.ATmega649P: Standby supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.125 6MHz_res 6MHz_xtal 0.115 0.105 4MHz_xtal 4MHz_res 0.095 0.085 ICC [mA] 31.8.6 0.075 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.065 0.055 0.
Pin pull-up Figure 31-442.Atmel ATmega649P: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 160 140 120 IOP [µA] 100 80 60 40 25°C 85°C -45°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] Figure 31-443.ATmega649P: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 50 IOP [µA] 31.8.7 40 30 20 10 25°C 0 85°C -45°C 0 0.5 1 1.5 2 2.
Figure 31-444.Atmel ATmega649P: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 35 IOP [µA] 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25°C 85°C -45°C 1.8 VOP [V] Figure 31-445.ATmega649P: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 120 105 IRESET [µA] 90 75 60 45 30 25°C -45°C 85°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-446.Atmel ATmega649P: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 54 48 IRESET [µA] 42 36 30 24 18 12 25°C -45°C 85°C 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET [V] Figure 31-447.ATmega649P: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 40 35 IRESET [µA] 30 25 20 15 10 25°C -45°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin driver strength Figure 31-448.Atmel ATmega649P: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 5V). 5.00 4.95 4.90 VOH [V] 4.85 4.80 4.75 -45°C 4.70 4.65 25°C 4.60 85°C 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 31-449.ATmega649P: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.7 2.6 2.5 2.4 VOH [V] 31.8.8 2.3 -45°C 2.2 2.1 25°C 2.0 85°C 1.
Figure 31-450.Atmel ATmega649P: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.8 1.7 VOH [V] 1.6 1.5 -45°C 1.4 25°C 1.3 85°C 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 31-451.ATmega649P: I/O pin output voltage vs. source current, port B (VCC= 5V). 5.0 4.9 VOH [V] 4.8 4.7 4.6 -45°C 4.5 25°C 85°C 4.4 4.
Figure 31-452.Atmel ATmega649P: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -45°C 1.8 25°C 1.6 1.4 85°C 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-453.ATmega649P: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.80 1.75 1.70 1.65 VOH [V] 1.60 1.55 1.50 -45°C 1.45 1.40 25°C 85°C 1.35 1.30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-454.Atmel ATmega649P: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 0.6 85°C 0.5 25°C 0.4 VOL [V] -45°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-455.ATmega649P. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -45°C 0.4 0.
Figure 31-456.Atmel ATmega649P: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). 0.32 85°C 25°C 0.28 0.24 -45°C VOL [V] 0.20 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 31-457.ATmega649P: I/O pin output voltage vs. sink current, port B (VCC = 5V). 0.6 85°C 25°C 0.5 -45°C VOL [V] 0.4 0.3 0.2 0.
Figure 31-458.Atmel ATmega649P: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C 1.0 25°C VOL [V] 0.8 -45°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-459.ATmega649P: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.50 85°C 0.45 25°C 0.40 0.35 -45°C VOL [V] 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Pin Threshold and Hysteresis Figure 31-460.Atmel ATmega649P: I/O pin input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.1 85°C 25°C -45°C 2.9 2.7 Threshold [V] 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-461.ATmega649P: I/O pin input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 2.4 85°C 25°C -45°C 2.2 2.0 1.8 Threshold [V] 31.8.9 1.6 1.4 1.2 1.0 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-462.Atmel ATmega649P: I/O pin input Hysteresis vs. VCC. 0.60 -45°C 0.55 Input Hysteresis [V] -45°C 0.50 25°C 0.45 0.40 85°C 0.35 0.30 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-463.ATmega649P: Reset input Threshold voltage vs. VCC (VIH, reset pin read as “1”). -45°C 25°C 85°C 2.4 2.2 Threshold [V] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-464.Atmel ATmega649P: Reset input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 85°C 25°C -45°C 2.4 2.2 2.0 Threshold [V] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-465.ATmega649P: Reset input pin Hysteresis vs. VCC. 0.7 Input Hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -45°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator offset Figure 31-466.Atmel ATmega649P: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.41 Rising Vcc BOD threshold [V] 4.39 4.37 4.35 Falling Vcc 4.33 4.31 4.29 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 75 85 Temperature [°C] Figure 31-467.ATmega649P: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.795 2.785 Rising Vcc 2.775 2.765 BOD threshold [V] 31.8.10 2.755 2.745 2.735 Falling Vcc 2.725 2.715 2.705 2.695 2.
Figure 31-468.Atmel ATmega649P: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.845 Rising Vcc 1.840 BOD threshold [V] 1.835 1.830 1.825 Falling Vcc 1.820 1.815 1.810 1.805 1.800 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-469.ATmega649P: Bandgap voltage vs. VCC. 1.103 1.101 Bandgap Voltage [V] 1.099 25°C 1.097 85°C 1.095 1.093 1.091 1.089 1.087 1.085 -45°C 1.083 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-470.Atmel ATmega649P: Bandgap voltage vs. temperature. 1.110 1.8V 1.108 3.3V Bandgap Voltage [V] 1.106 5.0V 1.104 5.5V 1.102 1.100 1.098 1.096 1.094 1.092 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Internal oscillator speed Figure 31-471.ATmega649P: Watchdog Oscillator frequency vs. VCC. 1290 -45°C 25°C 1260 85°C 1230 1200 FRC [kHz] 31.8.11 1170 1140 1110 1080 1050 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-472.Atmel ATmega649P: Watchdog Oscillator frequency vs. temperature. 1290 1260 5.5V 1230 5.0V FRC [kHz] 1200 4.5V 4.0V 3.3V 2.7V 1170 1140 1110 1080 1.8V 1050 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-473.ATmega649P: Calibrated 8MHz RC oscillator frequency vs. temperature. 5.5V 4.0V 3.3V 2.7V 8.2 8.1 8.0 FRC [MHz] 7.9 1.8V 7.8 7.7 7.6 7.5 7.4 7.
Figure 31-474.Atmel ATmega649P: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.2 85°C 8.1 25°C 8.0 FRC [MHz] 7.9 -45°C 7.8 7.7 7.6 7.5 7.4 7.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-475.ATmega649P: Calibrated 8MHz RC oscillator frequency vs. Osccal value.
Current consumption of peripheral units Figure 31-476.Atmel ATmega649P: Brownout Detector current vs. VCC. 42 39 36 33 ICC [µA] 30 27 85°C 25°C -45°C 24 21 18 15 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-477.ATmega649P: Active supply current with ADC at 50kHz vs. VCC. 85°C 25°C -45°C 330 300 270 ICC [µA] 31.8.12 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-478.Atmel ATmega649P: Active supply current with ADC at 200kHz vs. VCC. 360 85°C 25°C -45°C 330 300 ICC [µA] 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-479.ATmega649P: Active supply current with ADC at 1MHz vs. VCC. 340 85°C 25°C -45°C 310 ICC [µA] 280 250 220 190 160 130 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-480.Atmel ATmega649P: AREF external reference current vs. VCC. 170 85°C 25°C -45°C 155 140 ICC [µA] 125 110 95 80 65 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-481.ATmega649P: Watchdog Timer current vs. VCC. 18 85°C 25°C -45°C 16 14 ICC [µA] 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-482.Atmel ATmega649P: Analog Comparator current vs. VCC. 110 25°C 100 85°C 90 ICC [µA] 80 -45°C 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-483.ATmega649P: Programming current vs. VCC. 20 -45°C 18 16 ICC [mA] 14 25°C 12 10 85°C 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current consumption in Reset and Reset Pulswidth Figure 31-484.Atmel ATmega649P: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pull-up). ICC [mA] 0.16 0.14 5.5V 0.12 5.0V 0.10 4.5V 4.0V 0.08 3.3V 0.06 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-485.ATmega649P: Reset supply current vs. VCC (1 - 20MHz, excluding current through the reset pullup). 2.4 5.5V 2.1 5.0V 1.8 4.5V 1.5 ICC [mA] 31.8.13 1.2 4.
Figure 31-486.Atmel ATmega649P: Minimum reset pulse width vs. VCC. 2400 2100 Pulsewidth [ns] 1800 1500 1200 900 600 85°C 25°C -45°C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.9 Atmel ATmega6490A 31.9.1 Active supply current Figure 31-487.ATmega6490A: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.2 5.5V 5.0V 1.0 4.5V 0.8 ICC [mA] 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-488.ATmega6490A: Active supply current vs. frequency (1 - 20MHz). 16 5.5V 14 5.0V 12 4.5V ICC [mA] 10 8 4.0V 6 3.3V 4 2.7V 2 1.
Figure 31-489.Atmel ATmega6490A: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 7 85°C 25°C -45°C 6 ICC [mA] 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-490.ATmega6490A: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 0.45 25°C 85°C -45°C 0.40 ICC [mA] 0.35 0.30 0.25 0.20 0.15 0.10 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-491.Atmel ATmega6490A: Active supply current vs. VCC (32kHz watch XTAL). 85°C 25°C -45°C 40 36 32 ICC [mA] 28 24 20 16 12 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-492.ATmega6490A: Idle supply current vs.low frequency (0.1 - 1.0MHz). 0.30 5.5V 0.27 5.0V 4.5V 0.24 0.21 ICC [mA] 31.9.2 0.18 4.0V 0.15 3.3V 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-493.Atmel ATmega6490A: Idle supply current vs. frequency (1 - 20MHz). 4.5 5.5V 4.0 5.0V 3.5 4.5V ICC [mA] 3.0 2.5 2.0 4.0V 1.5 3.3V 1.0 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 31-494.ATmega6490A: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.0 85°C 25°C -45°C 1.8 1.6 ICC [mA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-495.Atmel ATmega6490A: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 1.4 85°C 25°C -45°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-496.ATmega6490A: Idle supply current vs. VCC (32kHz watch XTAL). 9.5 85°C 8.5 25°C -45°C 7.5 ICC [mA] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.9.3 Atmel ATmega6490A: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-17.
Power-down supply current Figure 31-497.Atmel ATmega6490A: Power-down supply current vs. VCC (Watchdog Timer disabled). 2.4 85°C 2.2 2.0 1.8 ICC [µA] 1.6 1.4 1.2 1.0 0.8 25°C -45°C 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-498.ATmega6490A: Power-down supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -45°C 18 16 14 ICC [µA] 31.9.4 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-499.Atmel ATmega6490A: Power-down supply current vs. VCC (32kHz watch XTAL). 1.5 85°C 1.3 ICC [mA] 1.1 0.9 0.7 0.5 0.3 25°C -45°C 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Power-save supply current Figure 31-500.ATmega6490A: Power-save supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 2.5 85°C 2.3 2.1 1.9 ICC [mA] 31.9.5 1.7 1.5 1.3 1.1 25°C 0.9 -45°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Standby supply current Figure 31-501.Atmel ATmega6490A standby supply current vs. VCC (32kHz watch XTAL, Watchdog Timer disabled). 2.5 85°C 2.3 2.1 ICC [mA] 1.9 1.7 1.5 1.3 1.1 25°C 0.9 -45°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-502.ATmega6490A: Standby supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.125 6MHz_res 6MHz_xtal 0.115 0.105 4MHz_xtal 4MHz_res 0.095 0.085 ICC [mA] 31.9.6 0.075 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.065 0.055 0.
Pin pull-up Figure 31-503.Atmel ATmega6490A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 160 140 120 IOP [µA] 100 80 60 40 25°C 85°C -45°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] Figure 31-504.ATmega6490A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 50 IOP [µA] 31.9.7 40 30 20 10 25°C 0 85°C -45°C 0 0.5 1 1.5 2 2.
Figure 31-505.Atmel ATmega6490A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 35 IOP [µA] 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25°C 85°C -45°C 1.8 VOP [V] Figure 31-506.ATmega6490A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 120 105 IRESET [µA] 90 75 60 45 30 25°C -45°C 85°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-507.Atmel ATmega6490A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 54 48 IRESET [µA] 42 36 30 24 18 12 25°C -45°C 85°C 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET [V] Figure 31-508.ATmega6490A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 40 35 IRESET [µA] 30 25 20 15 10 25°C -45°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin driver strength Figure 31-509.Atmel ATmega6490A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 5V). 5.00 4.95 4.90 VOH [V] 4.85 4.80 4.75 -45°C 4.70 4.65 25°C 4.60 85°C 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 31-510.ATmega6490A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 2.7V). 2.7 2.6 2.5 2.4 VOH [V] 31.9.8 2.3 -45°C 2.2 2.1 25°C 2.0 85°C 1.
Figure 31-511.Atmel ATmega6490A: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC = 1.8V). 1.8 1.7 VOH [V] 1.6 1.5 -45°C 1.4 25°C 1.3 85°C 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 31-512.ATmega6490A: I/O pin output voltage vs. source current, port B (VCC= 5V). 5.0 4.9 VOH [V] 4.8 4.7 4.6 -45°C 4.5 25°C 85°C 4.4 4.
Figure 31-513.Atmel ATmega6490A: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -45°C 1.8 25°C 1.6 1.4 85°C 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-514.ATmega6490A: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.80 1.75 1.70 1.65 VOH [V] 1.60 1.55 1.50 -45°C 1.45 1.40 25°C 85°C 1.35 1.30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-515.Atmel ATmega6490A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 0.6 85°C 0.5 25°C 0.4 VOL [V] -45°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-516.ATmega6490A. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -45°C 0.4 0.
Figure 31-517.Atmel ATmega6490A: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). 0.32 85°C 25°C 0.28 0.24 -45°C VOL [V] 0.20 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 31-518.ATmega6490A: I/O pin output voltage vs. sink current, port B (VCC = 5V). 0.6 85°C 25°C 0.5 -45°C VOL [V] 0.4 0.3 0.2 0.
Figure 31-519.Atmel ATmega6490A: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C 1.0 25°C VOL [V] 0.8 -45°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-520.ATmega6490A: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.50 85°C 0.45 25°C 0.40 0.35 -45°C VOL [V] 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Pin Threshold and Hysteresis Figure 31-521.Atmel ATmega6490A: I/O pin input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.1 85°C 25°C -45°C 2.9 2.7 Threshold [V] 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-522.ATmega6490A: I/O pin input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 2.4 85°C 25°C -45°C 2.2 2.0 1.8 Threshold [V] 31.9.9 1.6 1.4 1.2 1.0 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-523.Atmel ATmega6490A: I/O pin input Hysteresis vs. VCC. 0.60 -45°C 0.55 Input Hysteresis [V] -45°C 0.50 25°C 0.45 0.40 85°C 0.35 0.30 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-524.ATmega6490A: Reset input Threshold voltage vs. VCC (VIH, reset pin read as “1”). -45°C 25°C 85°C 2.4 2.2 Threshold [V] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-525.Atmel ATmega6490A: Reset input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 85°C 25°C -45°C 2.4 2.2 2.0 Threshold [V] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-526.ATmega6490A: Reset input pin Hysteresis vs. VCC. 0.7 Input Hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -45°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator offset Figure 31-527.Atmel ATmega6490A: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.41 Rising Vcc BOD threshold [V] 4.39 4.37 4.35 Falling Vcc 4.33 4.31 4.29 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-528.ATmega6490A: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.795 2.785 Rising Vcc 2.775 2.765 BOD threshold [V] 31.9.10 2.755 2.745 2.735 Falling Vcc 2.725 2.715 2.705 2.695 2.
Figure 31-529.Atmel ATmega6490A: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.845 Rising Vcc 1.840 BOD threshold [V] 1.835 1.830 1.825 Falling Vcc 1.820 1.815 1.810 1.805 1.800 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-530.ATmega6490A: Bandgap voltage vs. VCC. 1.103 1.101 Bandgap Voltage [V] 1.099 25°C 1.097 85°C 1.095 1.093 1.091 1.089 1.087 1.085 -45°C 1.083 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-531.Atmel ATmega6490A: Bandgap voltage vs. temperature. 1.110 1.8V 1.108 3.3V Bandgap Voltage [V] 1.106 5.0V 1.104 5.5V 1.102 1.100 1.098 1.096 1.094 1.092 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Internal oscillator speed Figure 31-532.ATmega6490A: Watchdog Oscillator frequency vs. VCC. 1290 -45°C 25°C 1260 85°C 1230 1200 FRC [kHz] 31.9.11 1170 1140 1110 1080 1050 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-533.Atmel ATmega6490A: Watchdog Oscillator frequency vs. temperature. 1290 1260 5.5V 1230 5.0V FRC [kHz] 1200 4.5V 4.0V 3.3V 2.7V 1170 1140 1110 1080 1.8V 1050 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-534.ATmega6490A: Calibrated 8MHz RC oscillator frequency vs. temperature. 5.5V 4.0V 3.3V 2.7V 8.2 8.1 8.0 FRC [MHz] 7.9 1.8V 7.8 7.7 7.6 7.5 7.4 7.
Figure 31-535.Atmel ATmega6490A: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.2 85°C 8.1 25°C 8.0 FRC [MHz] 7.9 -45°C 7.8 7.7 7.6 7.5 7.4 7.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-536.ATmega6490A: Calibrated 8MHz RC oscillator frequency vs. Osccal value.
Current consumption of peripheral units Figure 31-537.Atmel ATmega6490A: Brownout Detector current vs. VCC. 42 39 36 33 ICC [µA] 30 27 85°C 25°C -45°C 24 21 18 15 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-538.ATmega6490A: Active supply current with ADC at 50kHz vs. VCC. 85°C 25°C -45°C 330 300 270 ICC [µA] 31.9.12 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-539.Atmel ATmega6490A: Active supply current with ADC at 200kHz vs. VCC. 360 85°C 25°C -45°C 330 300 ICC [µA] 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-540.ATmega6490A: Active supply current with ADC at 1MHz vs. VCC. 340 85°C 25°C -45°C 310 ICC [µA] 280 250 220 190 160 130 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-541.Atmel ATmega6490A: AREF external reference current vs. VCC. 170 85°C 25°C -45°C 155 140 ICC [µA] 125 110 95 80 65 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-542.ATmega6490A: Watchdog Timer current vs. VCC. 18 85°C 25°C -45°C 16 14 ICC [µA] 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-543.Atmel ATmega6490A: Analog Comparator current vs. VCC. 110 25°C 100 85°C 90 ICC [µA] 80 -45°C 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-544.ATmega6490A: Programming current vs. VCC. 20 -45°C 18 16 ICC [mA] 14 25°C 12 10 85°C 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current consumption in Reset and Reset Pulswidth Figure 31-545.Atmel ATmega6490A: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pull-up). ICC [mA] 0.16 0.14 5.5V 0.12 5.0V 0.10 4.5V 4.0V 0.08 3.3V 0.06 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-546.ATmega6490A: Reset supply current vs. VCC (1 - 20MHz, excluding current through the reset pullup). 2.4 5.5V 2.1 5.0V 1.8 4.5V 1.5 ICC [mA] 31.9.13 1.2 4.
Figure 31-547.Atmel ATmega6490A: Minimum reset pulse width vs. VCC. 2400 2100 Pulsewidth [ns] 1800 1500 1200 900 600 85°C 25°C -45°C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.10 Atmel ATmega6490P Active supply current Figure 31-548.ATmega6490P: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.2 5.5V 5.0V 1.0 4.5V 0.8 ICC [mA] 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-549.ATmega6490P: Active supply current vs. frequency (1 - 20MHz). 16 5.5V 14 5.0V 12 4.5V 10 ICC [mA] 31.10.1 8 4.0V 6 3.3V 4 2.7V 2 1.
Figure 31-550.Atmel ATmega6490P: Active supply current vs. VCC (Internal RC oscillator, 8MHz). 7 85°C 25°C -45°C 6 ICC [mA] 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-551.ATmega6490P: Active supply current vs. VCC (Internal RC oscillator, 1MHz). 0.45 25°C 85°C -45°C 0.40 ICC [mA] 0.35 0.30 0.25 0.20 0.15 0.10 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-552.Atmel ATmega6490P: Active supply current vs. VCC (32kHz watch XTAL). 85°C 25°C -45°C 40 36 32 ICC [mA] 28 24 20 16 12 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Idle supply current Figure 31-553.ATmega6490P: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.30 5.5V 0.27 5.0V 4.5V 0.24 0.21 ICC [mA] 31.10.2 0.18 4.0V 0.15 3.3V 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-554.Atmel ATmega6490P: Idle supply current vs. frequency (1 - 20MHz). 16 5.5V 14 5.0V 12 4.5V ICC [mA] 10 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 31-555.ATmega6490P: Idle supply current vs. VCC (Internal RC oscillator, 8MHz). 2.0 85°C 25°C -45°C 1.8 1.6 ICC [mA] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-556.Atmel ATmega6490P: Idle supply current vs. VCC (Internal RC oscillator, 1MHz). 1.4 85°C 25°C -45°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-557.ATmega6490P: Idle supply current vs. VCC (32kHz watch XTAL). 9.5 85°C 8.5 25°C -45°C 7.5 ICC [mA] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.10.3 Atmel ATmega6490P: Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 45 for details. Table 31-19. Additional current consumption for the different I/O modules (absolute values).
Power-down supply current Figure 31-558.Atmel ATmega6490P: Power-down supply current vs. VCC (Watchdog Timer disabled). 2.4 85°C 2.2 2.0 1.8 ICC [µA] 1.6 1.4 1.2 1.0 0.8 25°C -45°C 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-559.ATmega6490P: Power-down supply current vs. VCC (Watchdog Timer enabled). 20 85°C 25°C -45°C 18 16 14 ICC [µA] 31.10.4 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-560.Atmel ATmega649A: Power-down supply current vs. VCC (32kHz watch XTAL). 1.5 85°C 1.3 ICC [mA] 1.1 0.9 0.7 0.5 0.3 25°C -45°C 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Power-save supply current Figure 31-561.ATmega6490P: Power-save supply current vs. VCC (Watchdog Timer disabled and 32kHz XTAL oscillator running). 2.5 85°C 2.3 2.1 1.9 ICC [mA] 31.10.5 1.7 1.5 1.3 1.1 25°C 0.9 -45°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Standby supply current Figure 31-562.Atmel ATmega649A standby supply current vs. VCC (32kHz watch XTAL, Watchdog Timer disabled). 2.5 85°C 2.3 2.1 ICC [mA] 1.9 1.7 1.5 1.3 1.1 25°C 0.9 -45°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-563.ATmega6490P: Standby supply current vs. VCC (XTAL and resonator, Watchdog Timer disabled). 0.125 6MHz_res 6MHz_xtal 0.115 0.105 4MHz_xtal 4MHz_res 0.095 0.085 ICC [mA] 31.10.6 0.075 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.065 0.055 0.
Pin pull-up Figure 31-564.Atmel ATmega6490P: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 160 140 120 IOP [µA] 100 80 60 40 25°C 85°C -45°C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] Figure 31-565.ATmega6490P: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 50 IOP [µA] 31.10.7 40 30 20 10 25°C 0 85°C -45°C 0 0.5 1 1.5 2 2.
Figure 31-566.Atmel ATmega6490P: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 35 IOP [µA] 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25°C 85°C -45°C 1.8 VOP [V] Figure 31-567.ATmega649A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 120 105 IRESET [µA] 90 75 60 45 30 25°C -45°C 85°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-568.Atmel ATmega6490P: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 54 48 IRESET [µA] 42 36 30 24 18 12 25°C -45°C 85°C 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET [V] Figure 31-569.ATmega6490P: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 40 35 IRESET [µA] 30 25 20 15 10 25°C -45°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin driver strength Figure 31-570.Atmel ATmega6490P: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC=5V). 5.00 4.95 4.90 VOH [V] 4.85 4.80 4.75 -45°C 4.70 4.65 25°C 4.60 85°C 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 31-571.ATmega6490P: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC=2.7V). 2.7 2.6 2.5 2.4 VOH [V] 31.10.8 2.3 -45°C 2.2 2.1 25°C 2.0 85°C 1.
Figure 31-572.Atmel ATmega6490P: I/O pin output voltage vs. source current, ports A, C, D, E, F, G (VCC=1.8V). 1.8 1.7 VOH [V] 1.6 1.5 -45°C 1.4 25°C 1.3 85°C 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 31-573.ATmega6490P: I/O pin output voltage vs. source current, Port B (VCC= 5V). 5.0 4.9 VOH [V] 4.8 4.7 4.6 -45°C 4.5 25°C 85°C 4.4 4.
Figure 31-574.Atmel ATmega6490P: I/O pin output voltage vs. source current, port B (VCC = 2.7V). 2.8 2.6 2.4 VOH [V] 2.2 2.0 -45°C 1.8 25°C 1.6 1.4 85°C 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 31-575.ATmega6490P: I/O pin output voltage vs. source current, port B (VCC = 1.8V). 1.80 1.75 1.70 1.65 VOH [V] 1.60 1.55 1.50 -45°C 1.45 1.40 25°C 85°C 1.35 1.30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 31-576.Atmel ATmega6490P: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 5V). 0.6 85°C 0.5 25°C 0.4 VOL [V] -45°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 31-577.ATmega6490P. I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -45°C 0.4 0.
Figure 31-578.Atmel ATmega6490P: I/O pin output voltage vs. sink current, ports A, C, D, E, F, G (VCC = 1.8V). 0.32 85°C 25°C 0.28 0.24 -45°C VOL [V] 0.20 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 31-579.ATmega6490P: I/O pin output voltage vs. sink current, port B (VCC = 5V). 0.6 85°C 25°C 0.5 -45°C VOL [V] 0.4 0.3 0.2 0.
Figure 31-580.Atmel ATmega6490P: I/O pin output voltage vs. sink current, port B (VCC = 2.7V). 1.2 85°C 1.0 25°C VOL [V] 0.8 -45°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 31-581.ATmega6490P: I/O pin output voltage vs. sink current, port B (VCC = 1.8V). 0.50 85°C 0.45 25°C 0.40 0.35 -45°C VOL [V] 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Pin Threshold and Hysteresis Figure 31-582.Atmel ATmega6490P: I/O pin input Threshold voltage vs. VCC (VIH, I/O pin read as “1”). 3.1 85°C 25°C -45°C 2.9 2.7 Threshold [V] 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-583.ATmega6490P: I/O pin input Threshold voltage vs. VCC (VIL, I/O pin read as “0”). 2.4 85°C 25°C -45°C 2.2 2.0 1.8 Threshold [V] 31.10.9 1.6 1.4 1.2 1.0 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-584.Atmel ATmega6490P: I/O pin input Hysteresis vs. VCC. 0.60 -45°C 0.55 Input Hysteresis [V] -45°C 0.50 25°C 0.45 0.40 85°C 0.35 0.30 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-585.ATmega6490P: Reset input Threshold voltage vs. VCC (VIH, reset pin read as “1”). -45°C 25°C 85°C 2.4 2.2 Threshold [V] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-586.Atmel ATmega6490P: Reset input Threshold voltage vs. VCC (VIL, reset pin read as “0”). 85°C 25°C -45°C 2.4 2.2 2.0 Threshold [V] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-587.ATmega6490P: Reset input pin Hysteresis vs. VCC. 0.7 Input Hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -45°C 25°C 85°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.10.10 BOD Thresholds and Analog Comparator offset Figure 31-588.Atmel ATmega6490P: BOD Thresholds vs. temperature (BOD level is 4.3V). 4.41 Rising Vcc BOD threshold [V] 4.39 4.37 4.35 Falling Vcc 4.33 4.31 4.29 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-589.ATmega6490P: BOD Thresholds vs. temperature (BOD level is 2.7V). 2.795 2.785 Rising Vcc 2.775 BOD threshold [V] 2.765 2.755 2.745 2.735 Falling Vcc 2.725 2.715 2.705 2.695 2.
Figure 31-590.Atmel ATmega6490P: BOD Thresholds vs. temperature (BOD level is 1.8V). 1.845 Rising Vcc 1.840 BOD threshold [V] 1.835 1.830 1.825 Falling Vcc 1.820 1.815 1.810 1.805 1.800 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-591.ATmega6490P: Bandgap voltage vs. VCC. 1.103 1.101 Bandgap Voltage [V] 1.099 25°C 1.097 85°C 1.095 1.093 1.091 1.089 1.087 1.085 -45°C 1.083 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-592.Atmel ATmega6490P: Bandgap voltage vs. temperature. 1.110 1.8V 1.108 3.3V Bandgap Voltage [V] 1.106 5.0V 1.104 5.5V 1.102 1.100 1.098 1.096 1.094 1.092 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 31.10.11 Internal oscillator speed Figure 31-593.ATmega6490P: Watchdog Oscillator frequency vs. VCC. 1290 -45°C 25°C 1260 85°C 1230 FRC [kHz] 1200 1170 1140 1110 1080 1050 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-594.Atmel ATmega6490P: Watchdog Oscillator frequency vs. temperature. 1290 1260 5.5V 1230 5.0V FRC [kHz] 1200 4.5V 4.0V 3.3V 2.7V 1170 1140 1110 1080 1.8V 1050 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 31-595.ATmega6490P: Calibrated 8MHz RC oscillator frequency vs. temperature. 5.5V 4.0V 3.3V 2.7V 8.2 8.1 8.0 FRC [MHz] 7.9 1.8V 7.8 7.7 7.6 7.5 7.4 7.
Figure 31-596.Atmel ATmega6490P: Calibrated 8MHz RC oscillator frequency vs. VCC. 8.2 85°C 8.1 25°C 8.0 FRC [MHz] 7.9 -45°C 7.8 7.7 7.6 7.5 7.4 7.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-597.ATmega6490P: Calibrated 8MHz RC oscillator frequency vs. Osccal value.
31.10.12 Current consumption of peripheral units Figure 31-598.Atmel ATmega6490P: Brownout Detector current vs. VCC. 42 39 36 33 ICC [µA] 30 27 85°C 25°C -45°C 24 21 18 15 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-599.ATmega6490P: Active supply current with ADC at 50kHz vs. VCC. 85°C 25°C -45°C 330 300 ICC [µA] 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-600.Atmel ATmega6490P: Active supply current with ADC at 200kHz vs. VCC. 360 85°C 25°C -45°C 330 300 ICC [µA] 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-601.ATmega6490P: Active supply current with ADC at 1MHz vs. VCC. 340 85°C 25°C -45°C 310 ICC [µA] 280 250 220 190 160 130 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-602.Atmel ATmega6490P: AREF external reference current vs. VCC. 170 85°C 25°C -45°C 155 140 ICC [µA] 125 110 95 80 65 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-603.ATmega6490P: Watchdog Timer current vs. VCC. 18 85°C 25°C -45°C 16 14 ICC [µA] 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 31-604.Atmel ATmega6490P: Analog Comparator current vs. VCC. 110 25°C 100 85°C 90 ICC [µA] 80 -45°C 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 31-605.ATmega6490P: Programming current vs. VCC. 20 -45°C 18 16 ICC [mA] 14 25°C 12 10 85°C 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
31.10.13 Current consumption in Reset and Reset Pulswidth Figure 31-606.Atmel ATmega6490P: Reset supply current vs. VCC (0.1 - 1.0MHz, excluding current through the reset pull-up). ICC [mA] 0.16 0.14 5.5V 0.12 5.0V 0.10 4.5V 4.0V 0.08 3.3V 0.06 2.7V 0.04 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 31-607.ATmega6490P: Reset supply current vs. VCC (1 - 20MHz, excluding current through the reset pullup). 2.4 5.5V 2.1 5.0V 1.8 4.5V ICC [mA] 1.5 1.2 4.
Figure 31-608.Atmel ATmega6490P: Minimum reset pulse width vs. VCC. 2400 2100 Pulsewidth [ns] 1800 1500 1200 900 600 85°C 25°C -45°C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
32. Typical Characteristics – TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
Figure 32-2. ATmega169PA-105°C: Active Supply Current vs. Frequency (1 - 16MHz) 11 10 5.5 V 9 5.0 V 8 4.5 V ICC (mA) 7 6 4.0 V 5 4 3.3 V 3 2.7 V 2 1 1.8 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 32-3. ATmega169PA-105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 105 °C 85 °C 25 °C -45 °C 6 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-4. ATmega169PA-105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 25 °C 105 °C 85 °C -45 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-5. ATmega169PA-105°C: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 105 °C 85 °C 25 °C -45 °C 36 32 ICC (uA) 28 24 20 16 12 8 4 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 32-6. ATmega169PA-105°C: Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.25 5.5 V ICC (mA) 0.2 5.0 V 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 32-7. ATmega169PA-105°C: Idle Supply Current vs. Frequency (1 - 16MHz) ICC (mA) 32.1.2 3.5 5.5 V 3 5.0 V 2.5 4.5 V 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.
Figure 32-8. ATmega169PA-105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 25 °C 105 °C 85 °C -45 °C 1.75 1.5 ICC (mA) 1.25 1 0.75 0.5 0.25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-9. ATmega169PA-105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.37 105 °C 85 °C 25 °C -45 °C 0.34 0.31 ICC (mA) 0.28 0.25 0.22 0.19 0.16 0.13 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-10. ATmega169PA-105°C: Idle Supply Current vs. VCC (32kHz Watch Crystal) 12 105 °C 10 85 °C 25 °C -45 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 32-11. ATmega169PA-105°C: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 4 105 °C 3.5 3 2.5 ICC (uA) 32.1.3 2 1.5 85 °C 1 0.5 -45 °C 25 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-12. ATmega169PA-105°C: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 22 105 °C 20 85 °C 25 °C -45 °C 18 ICC (uA) 16 14 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 32-13. ATmega169PA-105°C: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 3.5 105 °C 3.1 2.7 2.3 ICC (uA) 32.1.4 85 °C 1.9 1.5 25 °C 1.1 -45 °C 0.7 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.1.5 Standby Supply Current Figure 32-14. ATmega169PA-105°C: Standby Supply Current vs. VCC (32 kHz Watch Crystal, Watchdog Timer Disabled) 4 105 °C 3.5 3 ICC (uA) 2.5 85 °C 2 1.5 25 °C -45 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 32-15. ATmega169PA-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 150 125 100 IOP (uA) 32.1.6 75 50 25 °C 85 °C -45 °C 105 °C 25 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 32-16. ATmega169PA-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 25 °C 85 °C -45 °C 105 °C 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 32-17. ATmega169PA-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (uA) 35 30 25 20 15 25 °C 85 °C -45 °C 105 °C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 32-18. ATmega169PA-105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET (uA) 90 75 60 45 30 25 °C 85 °C -45 °C 105 °C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) Figure 32-19. ATmega169PA-105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 54 48 IRESET (uA) 42 36 30 24 18 25 °C 85 °C -45 °C 105 °C 12 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
Figure 32-20. ATmega169PA-105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C 85 °C -45 °C 105 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V) Pin Driver Strength Figure 32-21. ATmega169PA-105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5 4.95 4.9 4.85 VOH (V) 32.1.7 4.8 4.75 -45 °C 4.7 25 °C 4.65 85 °C 105 °C 4.6 4.
Figure 32-22. ATmega169PA-105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.7 2.6 2.5 VOH (V) 2.4 2.3 -45 °C 2.2 25 °C 2.1 85 °C 105 °C 2 1.9 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 32-23. ATmega169PA-105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.8 1.75 1.7 VOH (V) 1.65 1.6 1.55 1.5 -45 °C 1.45 1.4 25 °C 1.35 85 °C 105 °C 1.3 0 0.5 1 1.5 2 2.5 3 3.
Figure 32-24. ATmega169PA-105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 5V) 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -45 °C 4.5 25 °C 85 °C 105 °C 4.4 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 32-25. ATmega169PA-105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH (V) 2.2 -45 °C 2 1.8 25 °C 1.6 85 °C 105 °C 1.4 1.
Figure 32-26. ATmega169PA-105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.85 1.8 1.75 1.7 VOH (V) 1.65 1.6 1.55 -45 °C 1.5 1.45 25 °C 85 °C 105 °C 1.4 1.35 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (mA) Figure 32-27. ATmega169PA-105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 105 °C 85 °C 0.5 25 °C VOL (V) 0.4 -45 °C 0.3 0.2 0.
Figure 32-28. ATmega169PA-105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) VOL (V) 1.2 105 °C 1 85 °C 0.8 25 °C 0.6 -45 °C 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 32-29. ATmega169PA-105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 105 °C 85 °C 0.5 0.45 0.4 25 °C 0.35 VOL (V) 0.3 -45 °C 0.25 0.2 0.15 0.1 0.05 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
Figure 32-30. ATmega169PA-105°C: I/O Pin Output Voltage vs. Sink Current, PortB (VCC= 5V) VOL (V) 0.7 0.6 105 °C 85 °C 0.5 25 °C 0.4 -45 °C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 32-31. ATmega169PA-105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.4 105 °C 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -45 °C 0.4 0.
Figure 32-32. ATmega169PA-105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.55 105 °C 85 °C 0.5 0.45 0.4 25 °C VOL (V) 0.35 0.3 -45 °C 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 IOL (mA) Pin Thresholds and Hysteresis Figure 32-33. ATmega169PA-105°C: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 -45 °C 25 °C 85 °C 105 °C 2.7 2.4 Threshold (V) 32.1.8 2.1 1.8 1.5 1.2 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-34. ATmega169PA-105°C: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.4 105 °C 85 °C 25 °C -45 °C 2.1 Threshold (V) 1.8 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-35. ATmega169PA-105°C: I/O Pin Input Hysteresis vs. VCC 0.65 -45 °C 25 °C 85 °C 105 °C 0.6 Input Hysteresis (V) 0.55 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-36. ATmega169PA-105°C: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 -45 °C 25 °C 85 °C 105 °C 2.3 Threshold (V) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-37. ATmega169PA-105°C: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.4 105 °C 85 °C 25 °C -45 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-38. ATmega169PA-105°C: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -45 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) BOD Thresholds and Analog Comparator Offset Figure 32-39. ATmega169PA-105°C: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.37 Rising Vcc 4.35 BOD threshold (V) 32.1.9 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.
Figure 32-40. ATmega169PA-105°C: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.767 Rising Vcc BOD threshold (V) 2.752 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.662 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 32-41. ATmega169PA-105°C: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.831 Rising Vcc 1.826 BOD threshold (V) 1.821 1.816 1.811 Falling Vcc 1.806 1.801 1.796 1.791 1.
Figure 32-42. ATmega169PA-105°C: Bandgap Voltage vs. VCC 1.105 1.1 85 °C 105 °C 25 °C Bandgap Voltage (V) 1.095 1.09 1.085 1.08 1.075 1.07 -45 °C 1.065 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-43. ATmega169PA-105°C: Bandgap Voltage vs. Temperature 1.102 1.8 V 2.7 V 3.3 V 4.0 V 5.0 V 5.5 V Bandgap Voltage (V) 1.097 1.092 1.087 1.082 1.077 1.072 1.
Internal Oscillator Speed Figure 32-44. ATmega169PA-105°C: Watchdog Oscillator Frequency vs. VCC 1275 -45 °C 25 °C 85 °C 105 °C 1245 1215 FRC (kHz) 1185 1155 1125 1095 1065 1035 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-45. ATmega169PA-105°C: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V 8.2 8.1 8 FRC (MHz) 32.1.10 7.9 7.8 7.7 7.6 7.
Figure 32-46. ATmega169PA-105°C: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 105 °C 85 °C 8.1 25 °C FRC (MHz) 8 7.9 7.8 -45 °C 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-47. ATmega169PA-105°C: Calibrated 8MHz RC Oscillator Frequency vs.
Current Consumption of Peripheral Units Figure 32-48. ATmega169PA-105°C: Brownout Detector Current vs. VCC 28 105 °C 85 °C ICC (uA) 26 24 25 °C 22 -45 °C 20 18 16 14 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-49. ATmega169PA-105°C: Active Supply Current with ADC at 50kHz vs. VCC 105 °C 85 °C 25 °C -45 °C 350 325 300 275 ICC (µA) 32.1.11 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-50. ATmega169PA-105°C: Active Supply Current with ADC at 200kHz vs. VCC 350 325 ICC (µA) 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 VCC (V) Figure 32-51. ATmega169PA-105°C: Active Supply Current with ADC at 1MHz vs. VCC 105 °C 85 °C 25 °C -45 °C 350 325 300 ICC (µA) 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-52. ATmega169PA-105°C: AREF External Reference Current vs. VCC 170 105 °C 85 °C 25 °C -45 °C 150 ICC (uA) 130 110 90 70 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-53. ATmega169PA-105°C: Watchdog Timer Current vs. VCC 27 105 °C 85 °C 25 °C -45 °C 24 21 ICC (uA) 18 15 12 9 6 3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-54. ATmega169PA-105°C: Analog Comparator Current vs. VCC 83 -45 °C 76 25 °C 105 °C 85 °C 69 ICC (uA) 62 55 48 41 34 27 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-55. ATmega169PA-105°C: Programming Current vs. VCC 14.5 -45 °C 25 °C 13 85 °C 105 °C 11.5 ICC (mA) 10 8.5 7 5.5 4 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 32-56. ATmega169PA-105°C: Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) 0.16 5.5 V 0.14 5.0 V 0.12 4.5 V ICC (mA) 0.1 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 32-57. ATmega169PA-105°C: Reset Supply Current vs. VCC (1 - 16 MHz, Excluding Current Through The Reset Pull-up) 2.1 5.5 V 1.8 5.0 V 1.5 ICC (mA) 32.1.12 4.
Figure 32-58. ATmega169PA-105°C: Minimum Reset Pulse Width vs. VCC 2400 2100 Pulsewidth (ns) 1800 1500 1200 900 105 °C 85 °C 25 °C -45 °C 600 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.2 32.2.1 ATmega329A Active Supply Current Figure 32-59. ATmega329A - 105C: Active Supply Current vs. Frequency (0.1 - 1.0MHz) Figure 32-60. ATmega329A - 105C: Active Supply Current vs. Frequency (1 - 16MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.
Figure 32-61. ATmega329A - 105C: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 105°C 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-62. ATmega329A - 105C: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 105°C -40°C 25°C 85°C 1.3 1.2 1.1 ICC [mA] 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-63. ATmega329A - 105C: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 105 °C 85 °C 25 °C -45 °C 36 32 ICC (uA) 28 24 20 16 12 8 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 32-64. ATmega329A - 105C: Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.34 5.5 V 0.3 5.0 V 0.26 Icc [mA] 32.2.2 4.5 V 0.22 4.0 V 0.18 0.14 3.3 V 2.7 V 0.1 1.8 V 0.06 0.02 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-65. ATmega329A - 105C: Idle Supply Current vs. Frequency (1 - 20MHz) 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC [MHz] 3 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 32-66. ATmega329A - 105C: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ICC [mA] 2.25 2 105°C 1.75 25°C 85°C -40°C 1.5 1.25 1 0.75 0.5 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-67. ATmega329A - 105C: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) ICC [mA] 0.5 0.45 85°C 105°C 25°C 0.4 -40°C 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-68. ATmega329A - 105C: Idle Supply Current vs. VCC (32kHz Watch Crystal) 12 105 °C 10 85 °C 25 °C -45 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Power-down Supply Current Figure 32-69. ATmega329A - 105C: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 8 105°C 7 6 ICC [µA] 5 4 3 2 85°C 1 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-70. ATmega329A - 105C: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 26 105°C 23 20 ICC [uA] 32.2.3 85°C 25°C -40°C 17 14 11 8 5 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.2.4 Power-save Supply Current Figure 32-71. ATmega329A - 105C: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 4.0 105°C 3.5 3.0 ICC (µA) 2.5 85°C 2.0 1.5 25°C -45°C 1.0 0.5 0.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby Supply Current Figure 32-72. ATmega329A - 105C: Standby Supply Current vs.
Pin Pull-up Figure 32-73. ATmega329A - 105C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 150 135 120 IOP [µA] 105 90 75 60 45 -40°C 25°C 85°C 105°C 30 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] Figure 32-74. ATmega329A - 105C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP [µA] 32.2.6 50 40 30 20 -40°C 25°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
Figure 32-75. ATmega329A - 105C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 54 48 42 IOP [µA] 36 30 24 18 -40°C 25°C 85°C 105°C 12 6 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP [V] Figure 32-76. ATmega329A - 105C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET[µA] 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 32-77. ATmega329A - 105C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET[µA] 40 30 20 -40°C 25°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET [V] Figure 32-78. ATmega329A - 105C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET[µA] 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -40°C 25°C 85°C 105°C 1.
Pin Driver Strength Figure 32-79. ATmega329A - 105C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH [V] 4.9 4.85 4.8 4.75 -40°C 4.7 25°C 4.65 85°C 105°C 4.6 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 32-80. ATmega329A - 105C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 3V) 3 2.9 2.8 2.7 VOH [V] 32.2.7 -40°C 2.6 2.5 25°C 2.4 85°C 105°C 2.3 2.2 2.
Figure 32-81. ATmega329A - 105C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 1.7 VOH [V] 1.6 1.5 -40°C 1.4 25°C 85°C 105°C 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 32-82. ATmega329A - 105C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 5V) 5.1 5 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 105°C 4.
Figure 32-83. ATmega329A - 105C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 3V) 3.1 2.9 2.7 VOH [V] 2.5 -40°C 2.3 25°C 2.1 85°C 105°C 1.9 1.7 1.5 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 32-84. ATmega329A - 105C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.7 VOH [V] 1.6 1.5 -40°C 1.4 25°C 85°C 105°C 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 32-85. ATmega329A - 105C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.7 105°C 85°C 0.6 VOL [V] 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 32-86. ATmega329A - 105C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 3V) 1 105°C 0.9 85°C 0.8 0.7 25°C VOL [V] 0.6 -40°C 0.5 0.4 0.3 0.2 0.
Figure 32-87. ATmega329A - 105C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.36 105°C 85°C 0.32 0.28 25°C VOL [V] 0.24 0.2 -40°C 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 32-88. ATmega329A - 105C: I/O Pin Output Voltage vs. Sink Current, Port B(VCC= 5V) VOL [V] 0.7 0.6 105°C 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.
Figure 32-89. ATmega329A - 105C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 3V) 1.1 105°C 1 85°C 0.9 0.8 25°C VOL [V] 0.7 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 32-90. ATmega329A - 105C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.45 105°C 0.4 85°C 0.35 25°C VOL [V] 0.3 0.25 -40°C 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Pin Thresholds and Hysteresis Figure 32-91. ATmega329A - 105C: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.15 85 °C 105 °C -40 °C 25 °C 2.9 Threshold (V) 2.65 2.4 2.15 1.9 1.65 1.4 1.15 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-92. ATmega329A - 105C: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 105 °C 25 °C -40 °C 2.5 2.3 2.1 Threshold (V) 32.2.8 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-93. ATmega329A - 105C: I/O Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (V) 0.55 -40 °C 25 °C 85 °C 105 °C 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-94. ATmega329A - 105C: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 2.3 Threshold (V) 2.1 1.9 1.7 -40 °C 1.5 25 °C 1.3 85 °C 1.1 105 °C 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-95. ATmega329A - 105C: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.4 105 °C 85 °C 25 °C -40 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-96. ATmega329A - 105C: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (V) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator Offset Figure 32-97. ATmega329A - 105C: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.35 Rising Vcc BOD threshold [V] 4.33 4.31 4.29 Falling Vcc 4.27 4.25 4.23 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 32-98. ATmega329A - 105C: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.767 Rising Vcc 2.752 BOD threshold [V] 32.2.9 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.
Figure 32-99. ATmega329A - 105C: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.828 Rising Vcc BOD threshold [V] 1.823 1.818 1.813 1.808 Falling Vcc 1.803 1.798 1.793 1.788 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 32-100.ATmega329A - 105C: Bandgap Voltage vs. VCC Bandgap Voltage [V] 1.113 1.109 1.105 25°C 85°C 1.101 105°C 1.097 1.093 -40°C 1.089 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-101.ATmega329A - 105C: Bandgap Voltage vs. Temperature 1.116 Bandgap Voltage [V] 1.113 1.11 1.104 1.8V 4.0V 5.0V 1.101 5.5V 1.107 1.098 1.095 1.092 1.089 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Internal Oscillator Speed Figure 32-102.ATmega329A - 105C: Watchdog Oscillator Frequency vs. Temperature 1200 1180 5.5 V 1160 1140 FRC [kHz] 32.2.10 5.0 V 1120 4.5 V 1100 4.0 V 1080 3.3 V 1060 2.7 V 1040 1.
Figure 32-103.ATmega329A - 105C: Watchdog Oscillator Frequency vs. VCC -40°C 25°C 85°C 105°C 1200 1180 1160 FRC [kHz] 1140 1120 1100 1080 1060 1040 1020 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-104.AATmega329A - 105C: Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.05 5.5 V 4.0 V 2.7 V 1.8 V 1.03 FRC [MHz] 1.01 0.99 0.97 0.95 0.
Figure 32-105.ATmega329A - 105C: Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.05 105°C 85°C 1.035 FRC [MHz] 1.02 1.005 25°C 0.99 0.975 0.96 -40°C 0.945 0.93 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-106.AATmega329A - 105C: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.0 V 2.7 V 1.8 V 8.35 8.25 8.15 FRC [MHz] 8.05 7.95 7.85 7.75 7.65 7.55 7.
Figure 32-107.ATmega329A - 105C: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.35 105°C 8.25 85°C 8.15 FRC[MHz] 8.05 25°C 7.95 7.85 7.75 -40°C 7.65 7.55 7.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-108.ATmega329A - 105C: Calibrated 8MHz RC Oscillator Frequency vs.
Current Consumption of Peripheral Units Figure 32-109.ATmega329A - 105C: Brownout Detector Current vs. VCC 27 105°C 85°C 25 25°C ICC [µA] 23 -40°C 21 19 17 15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-110.ATmega329A - 105C: Active Supply Current with ADC at 50kHz vs. VCC -40°C 105°C 85°C 25°C 350 330 310 290 ICC [µA] 32.2.11 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-111.ATmega329A - 105C: Active Supply Current with ADC at 200kHz vs. VCC -40°C 25°C 85°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-112.ATmega329A - 105C: Active Supply Current with ADC at 1MHz vs. VCC -40°C 85°C 25°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-113.ATmega329A - 105C: Active Supply Current with ADC at 2MHz vs. VCC) -40°C 85°C 25°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-114.ATmega329A - 105C: AREF External Reference Current vs. VCC 105°C 85°C 25°C -40°C 165 150 135 ICC[uA] 120 105 90 75 60 45 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-115.ATmega329A - 105C: Watchdog Timer Current vs. VCC 19 85°C 105°C 25°C -40°C 17 15 ICC[µA] 13 11 9 7 5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-116.ATmega329A: - 105C Analog Comparator Current vs. VCC 87 -40°C 82 85°C 77 25°C ICC [µA] 72 105°C 67 62 57 52 47 42 37 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-117.ATmega329A - 105C: Programming Current vs. VCC 14 -40°C 25°C 13 ICC[mA] 12 11 85°C 10 105°C 9 8 7 6 5 4 3 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC[V] Current Consumption in Reset and Reset Pulsewidth Figure 32-118.ATmega329A - 105C: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) ICC [mA] 32.2.12 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-119.ATmega329A - 105C: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.4 5.5 V 2.1 5.0 V 1.8 ICC [mA] 4.5 V 1.5 1.2 4.0 V 0.9 0.6 3.3 V 2.7V 0.3 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 32-120.ATmega329A - 105C: Reset Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up and No Clock) 27 105°C 24 85°C 25°C -40°C 21 ICC[µA] 18 15 12 9 6 3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-121.ATmega329A - 105C: Minimum Reset Pulse Width vs. VCC 2300 Pulsewidth (ns) 2000 1700 1400 1100 800 105 °C 85 °C 25 °C -40 °C 500 200 1.5 2 2.5 3 3.5 4 4.5 5 5.
Active Supply Current Figure 32-122.ATmega329P-105°C: Active Supply Current vs. Frequency (0.1 - 1.0 MHz) 1.8 5.5 V 1.5 5.0 V 4.5 V 1.2 ICC (mA) 32.3.1 Typical characteristics ATmega329P 4.0 V 0.9 3.3 V 2.7 V 0.6 1.8 V 0.3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 32-123.ATmega329P-105°C: Active Supply Current vs. Frequency (1 - 20MHz) 24 5.5 V 21 5.0 V 18 4.5 V 15 ICC (mA) 32.3 12 4.0 V 9 3.3 V 6 2.7 V 3 1.
Figure 32-124.ATmega329P-105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 12 105 °C 85 °C 25 °C -40 °C 10 ICC (mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-125.ATmega329P-105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 2.1 105 °C 85 °C 25 °C -40 °C 1.8 ICC (mA) 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-126.ATmega329P-105°C: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 105 °C 85 °C 25 °C -40 °C 35 30 ICC (mA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 32-127.ATmega329P-105°C: Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.55 0.5 5.5 V 0.45 5.0 V 0.4 4.5 V 0.35 ICC (mA) 32.3.2 4.0 V 0.3 0.25 3.3 V 0.2 2.7 V 0.15 1.8 V 0.1 0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-128.ATmega329P-105°C: Idle Supply Current vs. Frequency (1 - 20MHz) 8 5.5 V 7 5.0 V 6 4.5 V ICC (mA) 5 4 4.0 V 3 3.3 V 2.7 V 2 1 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 32-129.ATmega329P-105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 3.5 105 °C 85 °C 25 °C -40 °C 3.2 2.9 ICC (mA) 2.6 2.3 2 1.7 1.4 1.1 0.8 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-130.ATmega329P-105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.9 105 °C 85 °C 25 °C -40 °C 0.8 ICC (mA) 0.7 0.6 0.5 0.4 0.3 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-131.ATmega329P-105°C: Idle Supply Current vs. VCC (32kHz Watch Crystal) 3 105 °C 2.5 ICC (mA) 2 1.5 85 °C 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Power-down Supply Current Figure 32-132.ATmega329P-105°C: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 6.5 105 °C 6 5.5 5 4.5 ICC (uA) 4 3.5 3 85 °C 2.5 2 1.5 -40 °C 25 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-133.ATmega329P-105°C: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 24 105 °C 20 85 °C 25 °C -40 °C 16 ICC (uA) 32.3.3 12 8 4 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.3.4 Power-save Supply Current Figure 32-134.ATmega329P -105°C: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 7 105 °C 6 ICC (uA) 5 4 85 °C 3 2 -40 °C 25 °C 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby Supply Current Figure 32-135.ATmega329P-105°C: Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 5 4.
Pin Pull-up Figure 32-136.ATmega329P-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP (uA) 100 80 60 25 °C 85 °C -40 °C 105 °C 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 32-137.ATmega329P-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 50 IOP (uA) 32.3.6 40 30 20 25 °C 85 °C -40 °C 105 °C 10 0 0 0.5 1 1.5 2 2.
Figure 32-138.ATmega329P-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 IOP (uA) 40 30 20 25 °C -40 °C 85 °C 105 °C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 32-139.ATmega329P-105°C: Reset Pull-up Resistor Current vs.
Figure 32-140.ATmega329P-105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 105 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 32-141.ATmega329P-105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (uA) 30 25 20 15 25 °C -40 °C 85 °C 105 °C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin Driver Strength Figure 32-142.ATmega329P-105°C: I/O Pin Output Voltage vs. Source Current, Ports A,C,D,E,F,G (VCC = 5V) 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 105 °C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 32-143.ATmega329P-105°C: I/O Pin Output Voltage vs. Source Current, Ports A,C,D,E,F,G (VCC = 3V) 3.2 3 2.8 VOH (V) 32.3.7 2.6 2.4 -40 °C 2.2 25 °C 2 85 °C 105 °C 1.
Figure 32-144.ATmega329P-105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 5V) 5 4.9 4.8 VOH (V) 4.7 4.6 4.5 4.4 -40 °C 4.3 25 °C 4.2 85 °C 105 °C 4.1 0 5 10 15 20 IOH (mA) Figure 32-145.ATmega329P-105°C: I/O Pin Output Voltage vs. Source Current, Port B(VCC = 3V) 3 VOH (V) 2.5 -40 °C 2 25 °C 1.5 85 °C 1 105 °C 0.
Figure 32-146.ATmega329P-105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC= 5V) VOL (V) 0.7 0.6 105 °C 85 °C 0.5 25 °C -40 °C 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 32-147.ATmega329P-105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 3V) 1 105 °C 85 °C 0.8 25 °C 0.6 VOL (V) -40 °C 0.4 0.
Figure 32-148.ATmega329P-105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) VOL (V) 1.4 1.2 105 °C 85 °C 1 25 °C 0.8 -40 °C 0.6 0.4 0.2 0 0 5 10 15 20 IOL (mA) Figure 32-149.ATmega329P-105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 3V) 1 105 °C 85 °C 0.9 0.8 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.
Pin Thresholds and Hysteresis Figure 32-150.ATmega329P-105°C: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 105 °C 85 °C -40 °C 25 °C Threshold (V) 2.5 2 1.5 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-151.ATmega329P-105°C: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.7 105 °C 85 °C 25 °C -40 °C 2.4 2.1 Threshold (V) 32.3.8 1.8 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-152.ATmega329P-105°C: I/O Pin Input Hysteresis vs. VCC 0.65 Input Hysteresis (mV) 0.6 -40 °C 25 °C 105 °C 85 °C 0.55 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-153.ATmega329P-105°C: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.4 -40 °C 25 °C 85 °C 105 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-154.ATmega329P-105°C: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.6 105 °C 85 °C 25 °C -40 °C 2.3 Threshold (V) 2 1.7 1.4 1.1 0.8 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-155.ATmega329P-105°C: Reset Input Pin Hysteresis vs. VCC 0.6 Input Hysteresis (mV) 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator Offset Figure 32-156.ATmega329P-105°C: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.32 Threshold (V) 4.3 Rising Vcc 4.28 4.26 Falling Vcc 4.24 4.22 4.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 32-157.ATmega329P-105°C: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.76 2.74 Threshold (V) 32.3.9 Rising Vcc 2.72 2.7 2.68 Falling Vcc 2.66 2.
Figure 32-158.ATmega329P-105°C: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.82 1.815 Rising Vcc 1.81 Threshold (V) 1.805 1.8 1.795 1.79 Falling Vcc 1.785 1.78 1.775 1.77 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) Figure 32-159.ATmega329P-105°C: Bandgap Voltage vs. VCC 1.08 105 °C 85 °C 1.075 Bandgap Voltage (V) 1.07 25 °C 1.065 1.06 1.055 -40 °C 1.05 1.045 1.04 1.7 2 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5 5.3 5.
Figure 32-160.ATmega329P-105°C: Bandgap Voltage vs. Temperature 1.08 4V 3.3V 1.8V 5V 5.5V Bandgap Voltage (V) 1.075 1.07 1.065 1.06 1.055 1.05 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Internal Oscillator Speed Figure 32-161.ATmega329P-105°C: Watchdog Oscillator Frequency vs. VCC 170 FRC (kHz) 32.3.10 165 -40 °C 25 °C 160 85 °C 105 °C 155 150 145 140 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-162.ATmega329P-105°C: Calibrated RC Oscillator Frequency vs. Temperature 8.3 8.1 5.5 V 4.5 V 3.3 V 2.7 V 8 1.8 V FRC (MHz) 8.2 7.9 7.8 7.7 7.6 7.5 7.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature Figure 32-163.ATmega329P-105°C: Calibrated RC Oscillator Frequency vs. VCC 8.4 8.3 105 °C 85 °C 8.2 FRC (MHz) 8.1 25 °C 8 7.9 -40 °C 7.8 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-164.ATmega329P-105°C: Calibrated RC Oscillator Frequency vs. Osccal Value 14 85 °C 105 °C 25 °C -40 °C 12 FRC (MHz) 10 8 6 4 2 0 20 40 60 80 100 120 140 160 180 200 220 240 260 OSCCAL (X1) Current Consumption of Peripheral Units Figure 32-165.ATmega329P-105°C: Brownout Detector Current vs. VCC 26 105 °C 85 °C 24 25 °C 22 ICC (uA) 32.3.11 -40 °C 20 18 16 14 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-166.ATmega329P-105°C: Active supply current with ADC vs. VCC 375 -40 °C 105 °C 85 °C 25 °C 350 325 ICC (uA) 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-167.ATmega329P-105°C: AREF External Reference Current 170 105 °C 85 °C 25 °C -40 °C 150 ICC (uA) 130 110 90 70 50 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-168.ATmega329P-105°C: Watchdog Timer Current vs. VCC 18 25 °C 105 °C 85 °C -40 °C 16 14 ICC (uA) 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-169.ATmega329P-105°C: Analog Comparator Current vs. VCC 90 -40 °C 25 °C 105 °C 85 °C 80 ICC (uA) 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-170.ATmega329P-105°C: Programming Current vs. VCC 12 -40 °C 25 °C 85 °C 105 °C 10 ICC (mA) 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Current Consumption in Reset and Reset Pulsewidth Figure 32-171.ATmega329P-105°C: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up 0.25 5.5 V 0.2 5.0 V 4.5 V ICC (mA) 32.3.12 0.15 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-172.ATmega329P-105°C: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) ICC (mA) 4.5 4 5.5 V 3.5 5.0 V 3 4.5 V 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 32-173.ATmega329P-105°C: Minimum Reset Pulse Width vs. VCC 2250 2000 Pulsewidth (ns) 1750 1500 1250 1000 750 105 °C 85 °C 25 °C -40 °C 500 250 0 1.5 2.5 3.5 4.5 5.
32.4 ATmega329PA - 105C 32.4.1 Active Supply Current Figure 32-174.ATmega329PA - 105C: Active Supply Current vs. Frequency (0.1 - 1.0MHz) Figure 32-175.ATmega329PA - 105C: Active Supply Current vs. Frequency (1 - 20MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.
Figure 32-176.ATmega329PA - 105C: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 105°C 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-177.ATmega329PA - 105C: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 105°C -40°C 25°C 85°C 1.3 1.2 1.1 ICC [mA] 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-178.ATmega329PA: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 105 °C 85 °C 25 °C -45 °C 36 32 ICC (uA) 28 24 20 16 12 8 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 32-179.ATmega329PA - 105C: Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.34 5.5 V 0.3 5.0 V 0.26 Icc [mA] 32.4.2 4.5 V 0.22 4.0 V 0.18 0.14 3.3 V 2.7 V 0.1 1.8 V 0.06 0.02 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-180.ATmega329PA - 105C: Idle Supply Current vs. Frequency (1 - 20MHz) 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC [MHz] 3 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 32-181.ATmega329PA - 105C: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ICC [mA] 2.25 2 105°C 1.75 25°C 85°C -40°C 1.5 1.25 1 0.75 0.5 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-182.ATmega329PA - 105C: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) ICC [mA] 0.5 0.45 85°C 105°C 25°C 0.4 -40°C 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-183.ATmega329PA - 105C: Idle Supply Current vs. VCC (32kHz Watch Crystal) 12 105 °C 10 85 °C 25 °C -45 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Power-down Supply Current Figure 32-184.ATmega329PA - 105C: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 8 105°C 7 6 ICC [µA] 5 4 3 2 85°C 1 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-185.ATmega329PA - 105C: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 26 105°C 23 20 ICC [uA] 32.4.3 85°C 25°C -40°C 17 14 11 8 5 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.4.4 Power-save Supply Current Figure 32-186.ATmega329PA - 105C: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 4.0 105°C 3.5 3.0 ICC (µA) 2.5 85°C 2.0 1.5 25°C -45°C 1.0 0.5 0.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby Supply Current Figure 32-187.ATmega329PA - 105C: Standby Supply Current vs.
Pin Pull-up Figure 32-188.ATmega329PA - 105C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 150 135 120 IOP [µA] 105 90 75 60 45 -40°C 25°C 85°C 105°C 30 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] Figure 32-189.ATmega329PA - 105C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP [µA] 32.4.6 50 40 30 20 -40°C 25°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
Figure 32-190.ATmega329PA - 105C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 54 48 42 IOP [µA] 36 30 24 18 -40°C 25°C 85°C 105°C 12 6 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP [V] Figure 32-191.ATmega329PA - 105C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET[µA] 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 32-192.ATmega329PA - 105C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET[µA] 40 30 20 -40°C 25°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET [V] Figure 32-193.ATmega329PA - 105C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET[µA] 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -40°C 25°C 85°C 105°C 1.
Pin Driver Strength Figure 32-194.ATmega329PA - 105C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH [V] 4.9 4.85 4.8 4.75 -40°C 4.7 25°C 4.65 85°C 105°C 4.6 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 32-195.ATmega329PA - 105C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 3V) 3 2.9 2.8 2.7 VOH [V] 32.4.7 -40°C 2.6 2.5 25°C 2.4 85°C 105°C 2.3 2.2 2.
Figure 32-196.ATmega329PA - 105C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 1.7 VOH [V] 1.6 1.5 -40°C 1.4 25°C 85°C 105°C 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 32-197.ATmega329PA - 105C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 5V) 5.1 5 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 105°C 4.
Figure 32-198.ATmega329PA - 105C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 3V) 3.1 2.9 2.7 VOH [V] 2.5 -40°C 2.3 25°C 2.1 85°C 105°C 1.9 1.7 1.5 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 32-199.ATmega329PA - 105C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.7 VOH [V] 1.6 1.5 -40°C 1.4 25°C 85°C 105°C 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 32-200.ATmega329PA - 105C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.7 105°C 85°C 0.6 VOL [V] 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 32-201.ATmega329PA - 105C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 3V) 1 105°C 0.9 85°C 0.8 0.7 25°C VOL [V] 0.6 -40°C 0.5 0.4 0.3 0.2 0.
Figure 32-202.ATmega329PA - 105C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.36 105°C 85°C 0.32 0.28 25°C VOL [V] 0.24 0.2 -40°C 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 32-203.ATmega329PA - 105C: I/O Pin Output Voltage vs. Sink Current, Port B(VCC= 5V) VOL [V] 0.7 0.6 105°C 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.
Figure 32-204.ATmega329PA - 105C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 3V) 1.1 105°C 1 85°C 0.9 0.8 25°C VOL [V] 0.7 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 32-205.ATmega329PA - 105C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.45 105°C 0.4 85°C 0.35 25°C VOL [V] 0.3 0.25 -40°C 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Pin Thresholds and Hysteresis Figure 32-206.ATmega329PA - 105C: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.15 85 °C 105 °C -40 °C 25 °C 2.9 Threshold (V) 2.65 2.4 2.15 1.9 1.65 1.4 1.15 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-207.ATmega329PA - 105C: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 105 °C 25 °C -40 °C 2.5 2.3 2.1 Threshold (V) 32.4.8 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-208.ATmega329PA - 105C: I/O Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (V) 0.55 -40 °C 25 °C 85 °C 105 °C 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-209.ATmega329PA - 105C: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 2.3 Threshold (V) 2.1 1.9 1.7 -40 °C 1.5 25 °C 1.3 85 °C 1.1 105 °C 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-210.ATmega329PA - 105C: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.4 105 °C 85 °C 25 °C -40 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-211.ATmega329PA - 105C: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (V) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator Offset Figure 32-212.ATmega329PA - 105C: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.35 Rising Vcc BOD threshold [V] 4.33 4.31 4.29 Falling Vcc 4.27 4.25 4.23 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 32-213.ATmega329PA - 105C: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.767 Rising Vcc 2.752 BOD threshold [V] 32.4.9 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.
Figure 32-214.ATmega329PA - 105C: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.828 Rising Vcc BOD threshold [V] 1.823 1.818 1.813 1.808 Falling Vcc 1.803 1.798 1.793 1.788 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 32-215.ATmega329PA - 105C: Bandgap Voltage vs. VCC Bandgap Voltage [V] 1.113 1.109 1.105 25°C 85°C 1.101 105°C 1.097 1.093 -40°C 1.089 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-216.ATmega329PA - 105C: Bandgap Voltage vs. Temperature 1.116 Bandgap Voltage [V] 1.113 1.11 1.104 1.8V 4.0V 5.0V 1.101 5.5V 1.107 1.098 1.095 1.092 1.089 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Internal Oscillator Speed Figure 32-217.ATmega329PA - 105C: Watchdog Oscillator Frequency vs. Temperature 1200 1180 5.5 V 1160 1140 FRC [kHz] 32.4.10 5.0 V 1120 4.5 V 1100 4.0 V 1080 3.3 V 1060 2.7 V 1040 1.
Figure 32-218.ATmega329PA - 105C: Watchdog Oscillator Frequency vs. VCC -40°C 25°C 85°C 105°C 1200 1180 1160 FRC [kHz] 1140 1120 1100 1080 1060 1040 1020 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-219.AATmega329PA - 105C: Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.05 5.5 V 4.0 V 2.7 V 1.8 V 1.03 FRC [MHz] 1.01 0.99 0.97 0.95 0.
Figure 32-220.ATmega329PA - 105C: Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.05 105°C 85°C 1.035 FRC [MHz] 1.02 1.005 25°C 0.99 0.975 0.96 -40°C 0.945 0.93 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-221.AATmega329PA - 105C: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.0 V 2.7 V 1.8 V 8.35 8.25 8.15 FRC [MHz] 8.05 7.95 7.85 7.75 7.65 7.55 7.
Figure 32-222.ATmega329PA - 105C: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.35 105°C 8.25 85°C 8.15 FRC[MHz] 8.05 25°C 7.95 7.85 7.75 -40°C 7.65 7.55 7.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-223.ATmega329PA - 105C: Calibrated 8MHz RC Oscillator Frequency vs.
Current Consumption of Peripheral Units Figure 32-224.ATmega329PA - 105C: Brownout Detector Current vs. VCC 27 105°C 85°C 25 25°C ICC [µA] 23 -40°C 21 19 17 15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-225.ATmega329PA - 105C: Active Supply Current with ADC at 50kHz vs. VCC -40°C 105°C 85°C 25°C 350 330 310 290 ICC [µA] 32.4.11 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-226.ATmega329PA - 105C: Active Supply Current with ADC at 200kHz vs. VCC -40°C 25°C 85°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-227.ATmega329PA - 105C: Active Supply Current with ADC at 1MHz vs. VCC -40°C 85°C 25°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-228.ATmega329PA - 105C: Active Supply Current with ADC at 2MHz vs. VCC) -40°C 85°C 25°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-229.ATmega329PA - 105C: AREF External Reference Current vs. VCC 105°C 85°C 25°C -40°C 165 150 135 ICC[uA] 120 105 90 75 60 45 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-230.ATmega329PA - 105C: Watchdog Timer Current vs. VCC 19 85°C 105°C 25°C -40°C 17 15 ICC[µA] 13 11 9 7 5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-231.ATmega329PA - 105C: Analog Comparator Current vs. VCC 87 -40°C 82 85°C 77 25°C ICC [µA] 72 105°C 67 62 57 52 47 42 37 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-232.ATmega329PA - 105C: Programming Current vs. VCC 14 -40°C 25°C 13 ICC[mA] 12 11 85°C 10 105°C 9 8 7 6 5 4 3 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC[V] Current Consumption in Reset and Reset Pulsewidth Figure 32-233.ATmega329PA - 105C: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) ICC [mA] 32.4.12 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-234.ATmega329PA - 105C: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.4 5.5 V 2.1 5.0 V 1.8 ICC [mA] 4.5 V 1.5 1.2 4.0 V 0.9 0.6 3.3 V 2.7V 0.3 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 32-235.ATmega329PA - 105C: Reset Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pullup and No Clock) 27 105°C 24 85°C 25°C -40°C 21 ICC[µA] 18 15 12 9 6 3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-236.ATmega329PA - 105C: Minimum Reset Pulse Width vs. VCC 2300 Pulsewidth (ns) 2000 1700 1400 1100 800 105 °C 85 °C 25 °C -40 °C 500 200 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.5 ATmega3290A 32.5.1 Active Supply Current Figure 32-237.ATmega3290A - 105C: Active Supply Current vs. Frequency (0.1 - 1.0MHz) Figure 32-238.ATmega3290A - 105C: Active Supply Current vs. Frequency (1 - 16MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.
Figure 32-239.ATmega3290A - 105C: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 7 105°C 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-240.ATmega3290A - 105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)S 1.4 105°C -40°C 25°C 85°C 1.3 1.2 1.1 ICC [mA] 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-241.ATmega3290A - 105°C: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 105 °C 85 °C 25 °C -45 °C 36 32 ICC (uA) 28 24 20 16 12 8 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 32-242.ATmega3290A - 105°C: Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.34 5.5 V 0.3 5.0 V 0.26 Icc [mA] 32.5.2 4.5 V 0.22 4.0 V 0.18 0.14 3.3 V 2.7 V 0.1 1.8 V 0.06 0.02 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-243.ATmega3290A - 105°C: Idle Supply Current vs. Frequency (1 - 20MHz) 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC [MHz] 3 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 32-244.ATmega3290A - 105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ICC [mA] 2.25 2 105°C 1.75 25°C 85°C -40°C 1.5 1.25 1 0.75 0.5 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-245.ATmega3290A - 105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ICC [mA] 0.5 0.45 85°C 105°C 25°C 0.4 -40°C 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-246.ATmega3290A - 105°C: Idle Supply Current vs. VCC (32kHz Watch Crystal) 12 105 °C 10 85 °C 25 °C -45 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Power-down Supply Current Figure 32-247.ATmega3290A - 105°C: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 8 105°C 7 6 ICC [µA] 5 4 3 2 85°C 1 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-248.ATmega3290A - 105°C: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 26 105°C 23 20 ICC [uA] 32.5.3 85°C 25°C -40°C 17 14 11 8 5 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.5.4 Power-save Supply Current Figure 32-249.ATmega3290A - 105°C: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 4.0 105°C 3.5 3.0 ICC (µA) 2.5 85°C 2.0 1.5 25°C -45°C 1.0 0.5 0.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) The differential current consumption between Power-save with WD disabled and 32 kHz TOSC represents the current drawn by Timer/Counter2. Standby Supply Current Figure 32-250.ATmega3290A - 105°C: Standby Supply Current vs.
Pin Pull-up Figure 32-251.ATmega3290A - 105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 150 135 120 IOP [µA] 105 90 75 60 45 -40°C 25°C 85°C 105°C 30 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP [V] Figure 32-252.ATmega3290A - 105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP [µA] 32.5.6 50 40 30 20 -40°C 25°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
Figure 32-253.ATmega3290A - 105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 54 48 42 IOP [µA] 36 30 24 18 -40°C 25°C 85°C 105°C 12 6 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP [V] Figure 32-254.ATmega3290A - 105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET[µA] 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 32-255.ATmega3290A - 105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET[µA] 40 30 20 -40°C 25°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET [V] Figure 32-256.ATmega3290A - 105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET[µA] 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -40°C 25°C 85°C 105°C 1.
Pin Driver Strength Figure 32-257.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH [V] 4.9 4.85 4.8 4.75 -40°C 4.7 25°C 4.65 85°C 105°C 4.6 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 32-258.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 3V) 3 2.9 2.8 2.7 VOH [V] 32.5.7 -40°C 2.6 2.5 25°C 2.4 85°C 105°C 2.3 2.2 2.
Figure 32-259.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 1.7 VOH [V] 1.6 1.5 -40°C 1.4 25°C 85°C 105°C 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 32-260.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 5V) 5.1 5 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 105°C 4.
Figure 32-261.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 3V) 3.1 2.9 2.7 VOH [V] 2.5 -40°C 2.3 25°C 2.1 85°C 105°C 1.9 1.7 1.5 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 32-262.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.7 VOH [V] 1.6 1.5 -40°C 1.4 25°C 85°C 105°C 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 32-263.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.7 105°C 85°C 0.6 VOL [V] 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 32-264.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 3V) 1 105°C 0.9 85°C 0.8 0.7 25°C VOL [V] 0.6 -40°C 0.5 0.4 0.3 0.2 0.
Figure 32-265.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.36 105°C 85°C 0.32 0.28 25°C VOL [V] 0.24 0.2 -40°C 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 32-266.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Sink Current, Port B(VCC= 5V) VOL [V] 0.7 0.6 105°C 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.
Figure 32-267.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 3V) 1.1 105°C 1 85°C 0.9 0.8 25°C VOL [V] 0.7 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 32-268.ATmega3290A - 105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.45 105°C 0.4 85°C 0.35 25°C VOL [V] 0.3 0.25 -40°C 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Pin Thresholds and Hysteresis Figure 32-269.ATmega3290A - 105°C: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.15 85 °C 105 °C -40 °C 25 °C 2.9 Threshold (V) 2.65 2.4 2.15 1.9 1.65 1.4 1.15 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-270.ATmega3290A - 105°C: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 105 °C 25 °C -40 °C 2.5 2.3 2.1 Threshold (V) 32.5.8 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-271.ATmega3290A - 105°C: I/O Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (V) 0.55 -40 °C 25 °C 85 °C 105 °C 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-272.ATmega3290A - 105°C: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 2.3 Threshold (V) 2.1 1.9 1.7 -40 °C 1.5 25 °C 1.3 85 °C 1.1 105 °C 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-273.ATmega3290A - 105°C: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.4 105 °C 85 °C 25 °C -40 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-274.ATmega3290A - 105°C: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (V) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator Offset Figure 32-275.ATmega3290A - 105°C: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.35 Rising Vcc BOD threshold [V] 4.33 4.31 4.29 Falling Vcc 4.27 4.25 4.23 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 32-276.ATmega3290A - 105°C: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.767 Rising Vcc 2.752 BOD threshold [V] 32.5.9 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.
Figure 32-277.ATmega3290A - 105°C: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.828 Rising Vcc BOD threshold [V] 1.823 1.818 1.813 1.808 Falling Vcc 1.803 1.798 1.793 1.788 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 32-278.ATmega3290A - 105°C: Bandgap Voltage vs. VCC Bandgap Voltage [V] 1.113 1.109 1.105 25°C 85°C 1.101 105°C 1.097 1.093 -40°C 1.089 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-279.ATmega3290A: Bandgap Voltage vs. Temperature 1.116 Bandgap Voltage [V] 1.113 1.11 1.104 1.8V 4.0V 5.0V 1.101 5.5V 1.107 1.098 1.095 1.092 1.089 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Internal Oscillator Speed Figure 32-280.ATmega3290A - 105°C: Watchdog Oscillator Frequency vs. Temperature 1200 1180 5.5 V 1160 1140 FRC [kHz] 32.5.10 5.0 V 1120 4.5 V 1100 4.0 V 1080 3.3 V 1060 2.7 V 1040 1.
Figure 32-281.ATmega3290A - 105°C: Watchdog Oscillator Frequency vs. VCC -40°C 25°C 85°C 105°C 1200 1180 1160 FRC [kHz] 1140 1120 1100 1080 1060 1040 1020 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-282.ATmega3290A - 105°C: Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.05 5.5 V 4.0 V 2.7 V 1.8 V 1.03 FRC [MHz] 1.01 0.99 0.97 0.95 0.
Figure 32-283.ATmega3290A - 105°C: Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.05 105°C 85°C 1.035 FRC [MHz] 1.02 1.005 25°C 0.99 0.975 0.96 -40°C 0.945 0.93 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-284.AATmega3290A - 105°C: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.0 V 2.7 V 1.8 V 8.35 8.25 8.15 FRC [MHz] 8.05 7.95 7.85 7.75 7.65 7.55 7.
Figure 32-285.ATmega3290A - 105°C: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.35 105°C 8.25 85°C 8.15 FRC[MHz] 8.05 25°C 7.95 7.85 7.75 -40°C 7.65 7.55 7.45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-286.ATmega3290A - 105°C: Calibrated 8MHz RC Oscillator Frequency vs.
Current Consumption of Peripheral Units Figure 32-287.ATmega3290A - 105°C: Brownout Detector Current vs. VCC 27 105°C 85°C 25 25°C ICC [µA] 23 -40°C 21 19 17 15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-288.ATmega3290A - 105°C: Active Supply Current with ADC at 50kHz vs. VCC -40°C 105°C 85°C 25°C 350 330 310 290 ICC [µA] 32.5.11 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-289.ATmega3290A - 105°C: Active Supply Current with ADC at 200kHz vs. VCC -40°C 25°C 85°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-290.ATmega3290A - 105°C: Active Supply Current with ADC at 1MHz vs. VCC) -40°C 85°C 25°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-291.ATmega3290A - 105°C: Active Supply Current with ADC at 2MHz vs. VCC) -40°C 85°C 25°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-292.ATmega3290A - 105°C: AREF External Reference Current vs. VCC 105°C 85°C 25°C -40°C 165 150 135 ICC[uA] 120 105 90 75 60 45 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-293.ATmega3290A - 105°C: Watchdog Timer Current vs. VCC 19 85°C 105°C 25°C -40°C 17 15 ICC[µA] 13 11 9 7 5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-294.ATmega3290A - 105°C: Analog Comparator Current vs. VCC 87 -40°C 82 85°C 77 25°C ICC [µA] 72 105°C 67 62 57 52 47 42 37 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-295.ATmega3290A - 105°C: Programming Current vs. VCC 14 -40°C 25°C 13 ICC[mA] 12 11 85°C 10 105°C 9 8 7 6 5 4 3 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC[V] Current Consumption in Reset and Reset Pulsewidth Figure 32-296.ATmega3290A - 105°C: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) ICC [mA] 32.5.12 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-297.ATmega3290A - 105°C: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.4 5.5 V 2.1 5.0 V 1.8 ICC [mA] 4.5 V 1.5 1.2 4.0 V 0.9 0.6 3.3 V 2.7V 0.3 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 32-298.ATmega3290A - 105°C: Reset Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pullup and No Clock) 27 105°C 24 85°C 25°C -40°C 21 ICC[µA] 18 15 12 9 6 3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-299.ATmega3290A - 105°C: Minimum Reset Pulse Width vs. VCC 2300 Pulsewidth (ns) 2000 1700 1400 1100 800 105 °C 85 °C 25 °C -40 °C 500 200 1.5 2 2.5 3 3.5 4 4.5 5 5.
Active Supply Current Figure 32-300.ATmega3290P-105°C: Active Supply Current vs. Frequency (0.1 - 1.0MHz) 1.8 5.5 V 1.5 5.0 V 4.5 V 1.2 ICC (mA) 32.6.1 Typical characteristics ATmega3290P 4.0 V 0.9 3.3 V 2.7 V 0.6 1.8 V 0.3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 32-301.ATmega3290P-105°C: Active Supply Current vs. Frequency (1 - 20MHz) 24 5.5 V 21 5.0 V 18 4.5 V 15 ICC (mA) 32.6 12 4.0 V 9 3.3 V 6 2.7 V 3 1.
Figure 32-302.ATmega3290P-105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 12 105 °C 85 °C 25 °C -40 °C 10 ICC (mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-303.ATmega3290P-105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 2.1 105 °C 85 °C 25 °C -40 °C 1.8 ICC (mA) 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-304.ATmega3290P-105°C: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 105 °C 85 °C 25 °C -40 °C 35 30 ICC (mA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 32-305.ATmega3290P-105°C: Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.55 0.5 5.5 V 0.45 5.0 V 0.4 4.5 V 0.35 ICC (mA) 32.6.2 4.0 V 0.3 0.25 3.3 V 0.2 2.7 V 0.15 1.8 V 0.1 0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-306.ATmega3290P-105°C: Idle Supply Current vs. Frequency (1 - 20MHz) 8 5.5 V 7 5.0 V 6 4.5 V ICC (mA) 5 4 4.0 V 3 3.3 V 2.7 V 2 1 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 32-307.ATmega3290P-105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 3.5 105 °C 85 °C 25 °C -40 °C 3.2 2.9 ICC (mA) 2.6 2.3 2 1.7 1.4 1.1 0.8 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-308.ATmega3290P-105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.9 105 °C 85 °C 25 °C -40 °C 0.8 ICC (mA) 0.7 0.6 0.5 0.4 0.3 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-309.ATmega3290P-105°C: Idle Supply Current vs. VCC (32kHz Watch Crystal) 3 105 °C 2.5 ICC (mA) 2 1.5 85 °C 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Power-down Supply Current Figure 32-310.ATmega3290P-105°C: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 6.5 105 °C 6 5.5 5 4.5 ICC (uA) 4 3.5 3 85 °C 2.5 2 1.5 -40 °C 25 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-311.ATmega3290P-105°C: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 24 105 °C 20 85 °C 25 °C -40 °C 16 ICC (uA) 32.6.3 12 8 4 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.6.4 Power-save Supply Current Figure 32-312.ATmega3290P -105°C: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 7 105 °C 6 ICC (uA) 5 4 85 °C 3 2 -40 °C 25 °C 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. Standby Supply Current Figure 32-313.ATmega3290P-105°C: Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 5 4.
Pin Pull-up Figure 32-314.ATmega3290P-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP (uA) 100 80 60 25 °C 85 °C -40 °C 105 °C 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 32-315.ATmega3290P-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 50 IOP (uA) 32.6.6 40 30 20 25 °C 85 °C -40 °C 105 °C 10 0 0 0.5 1 1.5 2 2.
Figure 32-316.ATmega3290P-105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 IOP (uA) 40 30 20 25 °C -40 °C 85 °C 105 °C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 32-317.ATmega3290P-105°C: Reset Pull-up Resistor Current vs.
Figure 32-318.ATmega3290P-105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 105 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 32-319.ATmega3290P-105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (uA) 30 25 20 15 25 °C -40 °C 85 °C 105 °C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin Driver Strength Figure 32-320.ATmega3290P-105°C: I/O Pin Output Voltage vs. Source Current, Ports A,C,D,E,G,G (VCC = 5V) 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 105 °C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 32-321.ATmega3290P-105°C: I/O Pin Output Voltage vs. Source Current, Ports A,C,D,E,G,G (VCC = 3V) 3.2 3 2.8 VOH (V) 32.6.7 2.6 2.4 -40 °C 2.2 25 °C 2 85 °C 105 °C 1.
Figure 32-322.ATmega3290P-105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 5V) 5 4.9 4.8 VOH (V) 4.7 4.6 4.5 4.4 -40 °C 4.3 25 °C 4.2 85 °C 105 °C 4.1 0 5 10 15 20 IOH (mA) Figure 32-323.ATmega3290P-105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 3V) 3 VOH (V) 2.5 -40 °C 2 25 °C 1.5 85 °C 1 105 °C 0.
Figure 32-324.ATmega3290P-105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC= 5V) VOL (V) 0.7 0.6 105 °C 85 °C 0.5 25 °C -40 °C 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 32-325.ATmega3290P-105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 3V) 1 105 °C 85 °C 0.8 25 °C 0.6 VOL (V) -40 °C 0.4 0.
Figure 32-326.ATmega3290P-105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) VOL (V) 1.4 1.2 105 °C 85 °C 1 25 °C 0.8 -40 °C 0.6 0.4 0.2 0 0 5 10 15 20 IOL (mA) Figure 32-327.ATmega3290P-105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 3V) 1 105 °C 85 °C 0.9 0.8 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.
Pin Thresholds and Hysteresis Figure 32-328.ATmega3290P-105°C: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 105 °C 85 °C -40 °C 25 °C Threshold (V) 2.5 2 1.5 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-329.ATmega3290P-105°C: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.7 105 °C 85 °C 25 °C -40 °C 2.4 2.1 Threshold (V) 32.6.8 1.8 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-330.ATmega3290P-105°C: I/O Pin Input Hysteresis vs. VCC 0.65 Input Hysteresis (mV) 0.6 -40 °C 25 °C 105 °C 85 °C 0.55 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-331.ATmega3290P-105°C: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.4 -40 °C 25 °C 85 °C 105 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-332.ATmega3290P-105°C: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.6 105 °C 85 °C 25 °C -40 °C 2.3 Threshold (V) 2 1.7 1.4 1.1 0.8 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-333.ATmega3290P-105°C: Reset Input Pin Hysteresis vs. VCC 0.6 Input Hysteresis (mV) 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator Offset Figure 32-334.ATmega3290P-105°C: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.32 Threshold (V) 4.3 Rising Vcc 4.28 4.26 Falling Vcc 4.24 4.22 4.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 32-335.ATmega3290P-105°C: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.76 2.74 Threshold (V) 32.6.9 Rising Vcc 2.72 2.7 2.68 Falling Vcc 2.66 2.
Figure 32-336.ATmega3290P-105°C: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.82 1.815 Rising Vcc 1.81 Threshold (V) 1.805 1.8 1.795 1.79 Falling Vcc 1.785 1.78 1.775 1.77 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (C) Figure 32-337.ATmega3290P-105°C: Bandgap Voltage vs. VCC 1.08 105 °C 85 °C 1.075 Bandgap Voltage (V) 1.07 25 °C 1.065 1.06 1.055 -40 °C 1.05 1.045 1.04 1.7 2 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5 5.3 5.
Figure 32-338.ATmega3290P-105°C: Bandgap Voltage vs. Temperature 1.08 4V 3.3V 1.8V 5V 5.5V Bandgap Voltage (V) 1.075 1.07 1.065 1.06 1.055 1.05 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Internal Oscillator Speed Figure 32-339.ATmega3290P-105°C: Watchdog Oscillator Frequency vs. VCC 170 FRC (kHz) 32.6.10 165 -40 °C 25 °C 160 85 °C 105 °C 155 150 145 140 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-340.ATmega3290P-105°C: Calibrated RC Oscillator Frequency vs. Temperature 8.3 8.1 5.5 V 4.5 V 3.3 V 2.7 V 8 1.8 V FRC (MHz) 8.2 7.9 7.8 7.7 7.6 7.5 7.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature Figure 32-341.ATmega3290P-105°C: Calibrated RC Oscillator Frequency vs. VCC 8.4 8.3 105 °C 85 °C 8.2 FRC (MHz) 8.1 25 °C 8 7.9 -40 °C 7.8 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-342.ATmega3290P-105°C: Calibrated RC Oscillator Frequency vs. Osccal Value 14 85 °C 105 °C 25 °C -40 °C 12 FRC (MHz) 10 8 6 4 2 0 20 40 60 80 100 120 140 160 180 200 220 240 260 OSCCAL (X1) Current Consumption of Peripheral Units Figure 32-343.ATmega3290P-105°C: Brownout Detector Current vs. VCC 26 105 °C 85 °C 24 25 °C 22 ICC (uA) 32.6.11 -40 °C 20 18 16 14 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-344.ATmega3290P-105°C: Active supply current with ADC vs. VCC 375 -40 °C 105 °C 85 °C 25 °C 350 325 ICC (uA) 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-345.ATmega3290P-105°C: AREF External Reference Current vs. VCC 170 105 °C 85 °C 25 °C -40 °C 150 ICC (uA) 130 110 90 70 50 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-346.ATmega3290P-105°C: Watchdog Timer Current vs. VCC 18 25 °C 105 °C 85 °C -40 °C 16 14 ICC (uA) 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-347.ATmega3290P-105°C: Analog Comparator Current vs. VCC 90 -40 °C 25 °C 105 °C 85 °C 80 ICC (uA) 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-348.ATmega3290P-105°C: Programming Current vs. VCC 12 -40 °C 25 °C 85 °C 105 °C 10 ICC (mA) 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Current Consumption in Reset and Reset Pulsewidth Figure 32-349.ATmega3290P-105°C: Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up 0.25 5.5 V 0.2 5.0 V 4.5 V ICC (mA) 32.6.12 0.15 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-350.ATmega3290P-105°C: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) ICC (mA) 4.5 4 5.5 V 3.5 5.0 V 3 4.5 V 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 32-351.ATmega3290P-105°C: Minimum Reset Pulse Width vs. VCC 2250 2000 Pulsewidth (ns) 1750 1500 1250 1000 750 105 °C 85 °C 25 °C -40 °C 500 250 0 1.5 2.5 3.5 4.5 5.
32.7 32.7.1 ATmega3290PA - 105°C Active Supply Current Figure 32-352.ATmega3290PA - 105C: Active Supply Current vs. Frequency (0.1 - 1.0MHz) Figure 32-353.ATmega3290PA - 105°C: Active Supply Current vs. Frequency (1 - 16MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.
Figure 32-354.ATmega3290PA - 105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 7 105°C 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-355.ATmega3290PA - 105°C: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)S 1.4 105°C -40°C 25°C 85°C 1.3 1.2 1.1 ICC [mA] 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-356.ATmega3290PA - 105°C: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 105 °C 85 °C 25 °C -45 °C 36 32 ICC (uA) 28 24 20 16 12 8 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 32-357.ATmega3290PA - 105°C: Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.34 5.5 V 0.3 5.0 V 0.26 Icc [mA] 32.7.2 4.5 V 0.22 4.0 V 0.18 0.14 3.3 V 2.7 V 0.1 1.8 V 0.06 0.02 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 32-358.ATmega3290PA - 105°C: Idle Supply Current vs. Frequency (1 - 20MHz) 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC [MHz] 3 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 32-359.ATmega3290PA - 105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ICC [mA] 2.25 2 105°C 1.75 25°C 85°C -40°C 1.5 1.25 1 0.75 0.5 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-360.ATmega3290PA - 105°C: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ICC [mA] 0.5 0.45 85°C 105°C 25°C 0.4 -40°C 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-361.ATmega3290PA - 105°C: Idle Supply Current vs. VCC (32kHz Watch Crystal) 12 105 °C 10 85 °C 25 °C -45 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Power-down Supply Current Figure 32-362.ATmega3290PA - 105°C: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 8 105°C 7 6 ICC [µA] 5 4 3 2 85°C 1 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-363.ATmega3290PA - 105°C: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 26 105°C 23 20 ICC [uA] 32.7.3 85°C 25°C -40°C 17 14 11 8 5 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
32.7.4 Power-save Supply Current Figure 32-364.ATmega3290PA - 105°C: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 4.0 105°C 3.5 3.0 ICC (µA) 2.5 85°C 2.0 1.5 25°C -45°C 1.0 0.5 0.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) The differential current consumption between Power-save with WD disabled and 32 kHz TOSC represents the current drawn by Timer/Counter2. Standby Supply Current Figure 32-365.ATmega3290PA - 105°C: Standby Supply Current vs.
Figure 32-366.ATmega3290PA: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) Pin Pull-up Figure 32-367.ATmega3290PA - 105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 150 135 120 105 IOP [µA] 32.7.6 90 75 60 45 -40°C 25°C 85°C 105°C 30 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 32-368.ATmega3290PA - 105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 IOP [µA] 60 50 40 30 20 -40°C 25°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOP [V] Figure 32-369.ATmega3290PA - 105°C: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 54 48 42 IOP [µA] 36 30 24 18 -40°C 25°C 85°C 105°C 12 6 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 32-370.ATmega3290PA - 105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET[µA] 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET [V] Figure 32-371.ATmega3290PA - 105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET[µA] 40 30 20 -40°C 25°C 85°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
Figure 32-372.ATmega3290PA - 105°C: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET[µA] 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -40°C 25°C 85°C 105°C 1.8 VRESET [V] Pin Driver Strength Figure 32-373.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G, H (VCC = 5V) 5.05 5 4.95 4.9 VOH [V] 32.7.7 4.85 4.8 4.75 -40°C 4.7 25°C 4.65 85°C 105°C 4.6 4.
Figure 32-374.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G, H (VCC = 3V) 3 2.9 2.8 VOH [V] 2.7 -40°C 2.6 2.5 25°C 2.4 85°C 105°C 2.3 2.2 2.1 2 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 32-375.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 1.7 VOH [V] 1.6 1.5 -40°C 1.4 25°C 85°C 105°C 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.
Figure 32-376.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 5V) 5.1 5 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 105°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 32-377.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 3V) 3.1 2.9 2.7 VOH [V] 2.5 -40°C 2.3 25°C 2.1 85°C 105°C 1.9 1.7 1.
Figure 32-378.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.7 VOH [V] 1.6 1.5 -40°C 1.4 25°C 85°C 105°C 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 32-379.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.7 105°C 85°C 0.6 VOL [V] 0.5 25°C 0.4 -40°C 0.3 0.2 0.
Figure 32-380.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 3V) 1 105°C 0.9 85°C 0.8 0.7 25°C VOL [V] 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 32-381.ATmega3290PA - 105°CATmega3290PA - 105°C: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.36 105°C 85°C 0.32 0.28 25°C VOL [V] 0.24 0.2 -40°C 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 32-382.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Sink Current, Port B(VCC= 5V) VOL [V] 0.7 0.6 105°C 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 32-383.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 3V) 1.1 105°C 1 85°C 0.9 0.8 25°C VOL [V] 0.7 0.6 -40°C 0.5 0.4 0.3 0.2 0.
Figure 32-384.ATmega3290PA - 105°C: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.45 105°C 0.4 85°C 0.35 25°C VOL [V] 0.3 0.25 -40°C 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOL [mA] Pin Thresholds and Hysteresis Figure 32-385.ATmega3290PA - 105°C: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.15 85 °C 105 °C -40 °C 25 °C 2.9 2.65 Threshold (V) 32.7.8 2.4 2.15 1.9 1.65 1.4 1.15 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-386.ATmega3290PA - 105°C: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 105 °C 25 °C -40 °C 2.5 2.3 Threshold (V) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-387.ATmega3290PA - 105°C: I/O Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (V) 0.55 -40 °C 25 °C 85 °C 105 °C 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-388.ATmega3290PA - 105°C: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 2.3 Threshold (V) 2.1 1.9 1.7 -40 °C 1.5 25 °C 1.3 85 °C 1.1 105 °C 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 32-389.ATmega3290PA - 105°C: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.4 105 °C 85 °C 25 °C -40 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-390.ATmega3290PA - 105°C: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (V) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 105 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) BOD Thresholds and Analog Comparator Offset Figure 32-391.ATmega3290PA - 105°C: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.35 Rising Vcc 4.33 BOD threshold [V] 32.7.9 4.31 4.29 Falling Vcc 4.27 4.25 4.
Figure 32-392.ATmega3290PA - 105°C: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.767 Rising Vcc BOD threshold [V] 2.752 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.662 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 32-393.ATmega3290PA - 105°C: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.828 Rising Vcc BOD threshold [V] 1.823 1.818 1.813 1.808 Falling Vcc 1.803 1.798 1.793 1.
Figure 32-394.ATmega3290PA - 105°C: Bandgap Voltage vs. VCC Bandgap Voltage [V] 1.113 1.109 1.105 25°C 85°C 1.101 105°C 1.097 1.093 -40°C 1.089 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] Figure 32-395.ATmega3290PA: Bandgap Voltage vs. Temperature 1.116 Bandgap Voltage [V] 1.113 1.11 1.104 1.8V 4.0V 5.0V 1.101 5.5V 1.107 1.098 1.095 1.092 1.
Internal Oscillator Speed Figure 32-396.ATmega3290PA - 105°C: Watchdog Oscillator Frequency vs. Temperature 1200 1180 5.5 V 1160 FRC [kHz] 1140 5.0 V 1120 4.5 V 1100 4.0 V 1080 3.3 V 1060 2.7 V 1040 1.8 V 1020 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C ] Figure 32-397.ATmega3290PA - 105°C: Watchdog Oscillator Frequency vs. VCC -40°C 25°C 85°C 105°C 1200 1180 1160 1140 FRC [kHz] 32.7.10 1120 1100 1080 1060 1040 1020 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-398.ATmega3290PA - 105°C: Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.05 5.5 V 4.0 V 2.7 V 1.8 V 1.03 FRC [MHz] 1.01 0.99 0.97 0.95 0.93 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C ] Figure 32-399.ATmega3290PA - 105°C: Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.05 105°C 85°C 1.035 FRC [MHz] 1.02 1.005 25°C 0.99 0.975 0.96 -40°C 0.945 0.93 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-400.AATmega3290PA - 105°C: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.0 V 2.7 V 1.8 V 8.35 8.25 8.15 FRC [MHz] 8.05 7.95 7.85 7.75 7.65 7.55 7.45 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 32-401.ATmega3290PA - 105°C: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.35 105°C 8.25 85°C 8.15 FRC[MHz] 8.05 25°C 7.95 7.85 7.75 -40°C 7.65 7.55 7.45 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-402.ATmega3290PA - 105°C: Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 17 105 °C 85 °C 25 °C -45 °C 15 FRC [MHz] 13 11 9 7 5 3 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] Current Consumption of Peripheral Units Figure 32-403.ATmega3290PA - 105°C: Brownout Detector Current vs. VCC 27 105°C 85°C 25 25°C 23 ICC [µA] 32.7.11 -40°C 21 19 17 15 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-404.ATmega3290PA - 105°C: Active Supply Current with ADC at 50kHz vs. VCC -40°C 105°C 85°C 25°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-405.ATmega3290PA - 105°C: Active Supply Current with ADC at 200kHz vs. VCC -40°C 25°C 85°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-406.ATmega3290PA - 105°C: Active Supply Current with ADC at 1MHz vs. VCC) -40°C 85°C 25°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-407.ATmega3290PA - 105°C: Active Supply Current with ADC at 2MHz vs. VCC) -40°C 85°C 25°C 105°C 350 330 310 ICC [µA] 290 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-408.ATmega3290PA - 105°C: AREF External Reference Current vs. VCC 105°C 85°C 25°C -40°C 165 150 135 ICC[uA] 120 105 90 75 60 45 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC[V] Figure 32-409.ATmega3290PA - 105°C: Watchdog Timer Current vs. VCC 19 85°C 105°C 25°C -40°C 17 15 ICC[µA] 13 11 9 7 5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 32-410.ATmega3290PA - 105°C: Analog Comparator Current vs. VCC 87 -40°C 82 85°C 77 25°C ICC [µA] 72 105°C 67 62 57 52 47 42 37 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-411.ATmega3290PA - 105°C: Programming Current vs. VCC 14 -40°C 25°C 13 ICC[mA] 12 11 85°C 10 105°C 9 8 7 6 5 4 3 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth ICC [mA] Figure 32-412.ATmega3290PA - 105°C: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 32-413.ATmega3290PA - 105°C: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.4 5.5 V 2.1 5.0 V 1.8 4.5 V ICC [mA] 32.7.
Figure 32-414.ATmega3290PA - 105°C: Reset Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up and No Clock) 27 105°C 24 85°C 25°C -40°C 21 ICC[µA] 18 15 12 9 6 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 32-415.ATmega3290PA - 105°C: Minimum Reset Pulse Width vs. VCC 2300 Pulsewidth (ns) 2000 1700 1400 1100 800 105 °C 85 °C 25 °C -40 °C 500 200 1.5 2 2.5 3 3.5 4 4.5 5 5.
33. Register summary Note: Address Registers with bold type only available in Atmel ATmega3290A/3290PA/6490A/6490P.
Address (0xC3) Name Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - - - Page (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 191 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 190 189 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - - - - - (0xBC) Reserved - - - - - - - -
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x82) TCCR1C Name FOC1A FOC1B - - - - - - 131 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 130 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 128 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 205 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 222 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 218
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x21 (0x41) EEARL EEPROM Address Register Low 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK PCIE PCIE2 PCIE1 PCIE0 0x1C (0x3C) EIFR PCIF3 PCIF2 PCIF1 0x1B (0x3B) Reserved - - - 0x1A (0x3A) Reserved - - 0x19 (0x39) Reserved - - 0x18 (0x38) Reserved - 0x17 (0x37) TIFR2 0x16 (0x36) - - - - EERIE Bit 2 Bit 1 Bit 0 Page 27 27 EEMWE EEWE EERE 27 - - - INT0 62 PC
34.
Mnemonics BRID Operands k Description Operation Flags #Clocks Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 RO
Mnemonics Operands Description Operation Flags #Clocks SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
35. Ordering information 35.1 Atmel ATmega169A Speed [MHz] (3) 16 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package type (1) ATmega169A-AU ATmega169A-AUR (4) ATmega169A-MU ATmega169A-MUR (4) ATmega169A-MCH ATmega169A-MCHR (4) 64A 64A 64M1 64M1 64MC 64MC ATmega169A-AN ATmega169A-ANR (4) ATmega169A-MN ATmega169A-MNR (4) 64A 64A 64M1 64M1 Operational range Industrial (-40C to 85C) Extended (-40C to 105C) 1. This device can also be supplied in wafer form.
35.2 Atmel ATmega169PA Speed [MHz] (3) 16 Notes: Power supply Ordering code (2) Package type(1) 64A 64A 64M1 64M1 64MC 64MC Industrial (-40C to 85C) 1.8 - 5.5V ATmega169PA-AU ATmega169PA-AUR(4) ATmega169PA-MU ATmega169PA-MUR(4) ATmega169PA-MCH ATmega169PA-MCHR(4) ATmega169PA-AN ATmega169PA-ANR(4) ATmega169PA-MN ATmega169PA-MNR(4) 64A 64A 64M1 64M1 Extended (-40C to 105C)(5) Operational range 1. This device can also be supplied in wafer form.
35.3 Atmel ATmega329A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package type (1) Operational range ATmega329A-AU ATmega329A-AUR (4) ATmega329A-MU ATmega329A-MUR (4) 64A 64A 64M1 64M1 Industrial (-40C to 85C) ATmega329A-AN ATmega329A-ANR (4) ATmega329A-MN ATmega329A-MNR (4) 64A 64A 64M1 64M1 Extended (-40C to 105C)(5) 1. This device can also be supplied in wafer form.
35.4 Atmel ATmega329PA Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package type (1) Operational range ATmega329PA-AU ATmega329PA-AUR(4) ATmega329PA-MU ATmega329PA-MUR(4) 64A 64A 64M1 64M1 Industrial (-40C to 85C) ATmega329PA-AN ATmega329PA-ANR(4) ATmega329PA-MN ATmega329PA-MNR(4) 64A 64A 64M1 64M1 Extended (-40C to 105C)(5) 1. This device can also be supplied in wafer form.
35.5 Atmel ATmega3290A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package type (1) Operational range ATmega3290A-AU ATmega3290A-AUR (4) 100A 100A Industrial (-40C to 85C) ATmega3290A-AN ATmega3290A-ANR (4) 100A 100A Extended (-40C to 105C)(5) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
35.6 Atmel ATmega3290PA Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package type (1) Operational range ATmega3290PA-AU ATmega3290PA-AUR(4) 100A 100A Industrial (-40C to 85C) ATmega3290PA-AN ATmega3290PA-ANR(4) 100A 100A Industrial (-40C to 105C)(5) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
35.7 Atmel ATmega649A Speed [MHz] (3) 16 Notes: Power supply 1.8 - 5.5V Ordering code (2) ATmega649A-AU ATmega649A-AUR (4) ATmega649A-MU ATmega649A-MUR (4) Package type (1) 64A 64A 64M1 64M1 Operational range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
35.8 Atmel ATmega649P Speed [MHz] (3) 16 Notes: Power supply 1.8 - 5.5 V Ordering code (2) ATmega649P-AU ATmega649P-AUR (4) ATmega649P-MU ATmega649P-MUR (4) Package type (1) 64A 64A 64M1 64M1 Operational range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
35.9 Atmel ATmega6490A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) ATmega6490A-AU ATmega6490A-AUR (4) Package type (1) 100A 100A Operational range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3.
35.10 Atmel ATmega6490P Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) ATmega6490P-AU ATmega6490P-AUR (4) Package type (1) 100A 100A Operational range Industrial (-40C to 85C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3.
36. Packaging Information 36.1 64A PIN 1 B PIN 1 e B PIN 1 IDENTIFIER e PIN 1 IDENTIFIER E1 E E1 E D1 D1 DD C C 0°~7° 0°~7° A1 A1 A2 A2 AA LL COMMON DIMENSIONS COMMON DIMENSIONS (Unit of of measure = mm) (Unit measure = mm) SYMBOL MIN SYMBOL MIN – – – A1 0.05 – A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 E 15.75 16.00 16.25 A A1 A2 D D1 Notes: E Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 1.
36.2 64M1 D D Marked Pin# 1 ID Marked Pin# 1 ID E E SEATING PLANE CSEATING PLANE C A1 A1 TOP VIEW TOP VIEW AA KK 0.08 C C 0.08 L L Pin Pin #1 #1 Corner Corner D2 D2 11 22 33 Option A Option SIDEVIEW VIEW SIDE Pin Pin#1 #1 Triangle Triangle COMMON DIMENSIONS COMMON DIMENSIONS (Unit of of Measure = mm) (Unit Measure = mm) SYMBOL MIN SYMBOL MIN E2E2 Option B Option B Pin #1 Pin #1 Chamfer Chamfer (C 0.30) (C 0.30) NOM NOM MAX MAX NOTE NOTE A A 0.80 0.80 0.90 1.00 A1 – 0.02 0.
64MC C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT eT/2 L A26 eR 36.3 A34 B23 B30 COMMON DIMENSIONS (Unit of Measure = mm) A1 A25 B1 B22 R0.20 0.40 b D2 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.28 C eT B7 B16 A8 A18 A9 A17 L (0.18) REF B8 B15 E2 K BOTTOM VIEW Note: 1. The terminal #1 ID is a Laser-marked Feature. Package Drawing Contact: packagedrawings@atmel.com (0.1) REF NOTE 0.20 REF D 6.90 7.00 7.10 D2 3.95 4.00 4.
36.4 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08mm maximum. MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.
37. Errata 37.1 Atmel ATmega169A No known errata 37.2 Atmel ATmega169A/169PA Rev. A to F Not sampled. 37.3 Atmel ATmega169PA Rev. G No known errata. 37.4 Atmel ATmega329A/329PA rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer • Using BOD disable will make the chip reset 1.
37.6 Atmel ATmega329A/329PA rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
37.9 Atmel ATmega3290A/3290PA rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
38. Datasheet revision history Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. 38.1 Rev. 8284E - 02/2013 1. 2. 3. 4. 5. 6. 7. 8. 9. 38.2 Rev. 8284D - 06/11 1. 2. 38.3 Removed “Preliminary” from the front page Updated the Table 29-16 on page 344. VPOT falling / Min. is 0.05V, not 0.5V Rev. 8284C - 06/11 1. 2. 38.
38.5 Rev. 8284A - 10/10 1.
Table of Contents Features ..................................................................................................... 1 1 Pin configurations .................................................................................... 2 1.1Pinout - 64A (TQFP) and 64M1 (QFN/MLF) ..............................................................2 1.2Pinout - 100A (TQFP) ................................................................................................3 1.3Pinout - 64MC (DRQFN) ...................
9.3Default clock source ................................................................................................30 9.4Calibrated internal RC oscillator ..............................................................................30 9.5XTAL oscillator ........................................................................................................31 9.6Low-frequency XTAL oscillator ................................................................................32 9.7External clock ...........
14 I/O-ports .................................................................................................. 65 14.1Overview ................................................................................................................65 14.2Ports as general digital I/O ....................................................................................66 14.3Alternate port functions ..........................................................................................71 14.4Register description ..
18.3Timer/Counter clock sources ...............................................................................142 18.4Counter Unit ........................................................................................................142 18.5Output Compare Unit ...........................................................................................143 18.6Compare Match Output Unit ................................................................................144 18.7Modes of Operation ................
22.3Register description .............................................................................................204 23 Analog to Digital Converter ................................................................. 206 23.1Features ..............................................................................................................206 23.2Overview ..............................................................................................................206 23.3Operation ....................
26.7Boundary-scan Description Language Files ........................................................276 26.8Register description .............................................................................................277 27 Boot Loader Support – Read-While-Write Self-Programming ......... 278 27.1Features ..............................................................................................................278 27.2Overview .......................................................................
30.2DC Characteristics ...............................................................................................339 31 Typical Characteristics – TA = -40°C to 85°C .................................... 344 31.1Atmel ATmega169A ............................................................................................344 31.2Atmel ATmega169PA ..........................................................................................376 31.3Atmel ATmega329A ..............................................
36.264M1 ....................................................................................................................889 36.364MC ...................................................................................................................890 36.4100A ....................................................................................................................891 37 Errata ..................................................................................................... 892 37.
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